ISL26312FVZ-T
ISL26312FVZ-T - 12-bit 125kSPS SAR ADC, 2-ch Diff | Renesas
The Renesas ISL26312FVZ-T is a 12-bit, 125 kSPS successive-approximation register (SAR) analog-to-digital converter with two differential input channels, offered in a 16-pin TSSOP package for industrial and instrumentation front-ends. As a member of the ISL26310/11/12/13/14/15/19 family, it provides excellent linearity across supply and temperature variations while consuming only 11 mW at full throughput and dropping to a typical 8 µA between conversions when auto power-down is enabled, making it well suited for battery-aware data-acquisition systems.
A SAR ADC is a converter architecture that performs a binary search through an internal capacitive charge-redistribution DAC, evaluating one bit per conversion clock and producing the result on a single clock cycle without requiring a pipeline delay. SAR ADCs are prized for low-latency triggering, deterministic behavior on multiplexed inputs, and excellent DC linearity with no missing codes - and they remain the dominant choice for multi-channel precision industrial front-ends where both sample-accurate acquisition and lowest idle power matter.
Key specifications of this part include 12-bit resolution, 125 kSPS maximum sampling rate, ±10 V input range when configured for bipolar operation, true-differential analog inputs, an SPI-compatible serial interface, single 2.7 V to 5.25 V supply operation, and automotive-grade -40 °C to +125 °C temperature support. The 0.7 LSB typical DNL, on-chip track-and-hold, and integrated input multiplexer enable direct sensor interfacing with minimal external signal conditioning.
The on-chip sequencer and auto power-down state machine, combined with a flexible analog input mux, make the ISL26312FVZ-T straightforward to drop into multiplexed sensor panels, isolated transducer front-ends, and process-control loops. The SPI port operates in mode 0 and mode 3 and is easily framed by most FPGAs, microcontrollers, and digital isolators, so a single part can serve both 3.3 V MCU rails and 5 V legacy PLC backplanes.
Typical uses include industrial process instrumentation, multi-channel data loggers, motor-control feedback, isolated sensor readouts, and precision weigh-scale / strain-gauge signal chains. The wide 2.7 V to 5.25 V supply range tolerates either a regulated 3.3 V rail or a 5 V USB- or PLC-derived supply. Across all of these uses, the TSSOP-16 footprint keeps the converter area cost low and routing simple.
When designing with this device, place a 100 nF decoupling capacitor within 5 mm of the AVDD pin and a 10 µF bulk capacitor on the analog supply, route the analog and digital grounds through a star tie at the AGND pin, and verify SPI mode (CPOL/CPHA) against the host controller. For low-distortion input buffers, an op-amp rail-to-output driver such as the OPA2188 is recommended to avoid degrading the converter's DNL.
This page combines distributor pricing, pin-compatible drop-in alternatives, and application design notes into a single reference - saving engineering time versus cross-checking three separate component databases.
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