MAX11627EEE/V+T
MAX11627EEE/V+T - 12-Bit 300ksps SAR ADC w/ FIFO | Maxim
The Maxim Integrated (Analog Devices) MAX11627EEE/V+T is a 12-bit, 300 ksps, low-power successive-approximation analog-to-digital converter with 4 analog input channels, an internal 2.5V reference, an internal 2.048 MHz oscillator, and a 16-entry FIFO housed in a 16-pin QSOP package. The /V suffix denotes the automotive-grade (AEC-Q100) screening, and the +T suffix denotes tape-and-reel packaging. The MAX11627 is part of a six-member family (MAX11626-MAX11629 and MAX11632/MAX11633) that shares a common serial interface and pinout but differs in channel count, reference voltage, and FIFO depth.
A successive-approximation register (SAR) ADC is a sampling converter architecture that performs one bit decision per internal clock cycle using a binary-search algorithm against a precision DAC. SAR ADCs are valued for deterministic latency, no pipeline delay, and excellent DC accuracy at moderate sample rates, placing them between low-speed delta-sigma converters and high-speed pipeline ADCs in the data-converter hierarchy. The 16-entry FIFO on the MAX11627 decouples the host sample rate from the conversion rate, allowing the host to sleep between block transfers and reducing SPI bus traffic in power-constrained or interrupt-driven embedded designs.
Key features include 4 single-ended analog inputs (0 to VREF range), 12-bit resolution with ±1 LSB INL and ±1 LSB DNL and no missing codes over temperature, 300 ksps maximum throughput, an internal 2.5V reference, scan-mode auto-sequencing, internal averaging, 10 MHz SPI/QSPI/MICROWIRE-compatible serial interface, an internal clock that eliminates an external crystal, and a low 2.7V-3.6V analog supply. The /V automotive variant adds extended qualification per AEC-Q100, suiting the part for body-electronics, sensor, and industrial-sensor applications where -40C to +85C operation is required.
Typical applications include automotive sensor interfaces (e.g., pedal position, throttle, HVAC flap position), industrial multi-channel data-acquisition modules, battery-monitoring systems for 12V/24V lead-acid and lithium packs, portable instrumentation front ends, and any 3.3V-rail embedded design that needs 12-bit multi-channel conversion with host-monitored data movement. The internal reference and internal clock minimize external BOM, while the FIFO reduces microcontroller wake-up frequency for power-budget-sensitive applications.
When designing with the MAX11627EEE/V+T, place the 0.1 uF + 10 uF decoupling pair as close as possible to AVDD and DVDD pins, keep the analog input traces short and guarded, and bypass REF with the 10 uF capacitor recommended in the manufacturer datasheet. The internal reference can source up to 1 mA, so any external load beyond ratiometric must be buffered.
This page synthesizes distributor pricing, FIFO-aware firmware design notes, AEC-Q100 qualification details, and drop-in replacement options not aggregated in the manufacturer datasheet, providing a single engineering decision surface for embedded design teams evaluating the MAX11627 family.
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