10M08DCV81I7G vs 10M08DCV81C7G 比較
詳細な並列比較: 10M08DCV81I7G メーカー: Altera および 10M08DCV81C7G メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | 10M08DCV81I7G | 10M08DCV81C7G |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $26.85 | $16.20 |
| Product Family | MAX 10 | — |
| Logic Elements (LE) | 8000 | 8000 |
| Embedded User Flash | 387072 bit (378 Kbit) | — |
| Maximum User I/Os | 56 | — |
| Package Type | 81-ball WLCSP (UFBGA, wafer-level chip-scale package) | — |
| Process Node | [DATA_NEEDED: process node] | — |
| Configuration Memory | On-chip dual-configuration flash, instant-on | — |
| Embedded ADC | 12-bit SAR ADC (1 Msps) [DATA_NEEDED: number of channels] | — |
| 動作温度 | Industrial -40C to +100C (I7 grade) | Commercial (0C to +85C) [DATA_NEEDED: temp grade letter C7G] |
| Supply Voltage Core | [DATA_NEEDED: VCC core voltage] | — |
| I/O Bank Count | [DATA_NEEDED: number of I/O banks] | — |
| I/O Standards Supported | LVCMOS, LVTTL, LVDS, SSTL, RSDS | — |
| Memory Interfaces | DDR3, DDR3L, LPDDR2 (external PHY required) | — |
| PLL Count | [DATA_NEEDED: number of PLLs] | — |
| Global Clock Networks | [DATA_NEEDED: clock network count] | — |
| Configuration Modes | JTAG, Active Serial (AS), Passive Serial (PS) | — |
| 実装タイプ | Surface Mount (WLCSP - requires underfill) | Surface Mount |
| MSLレベル | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL rating] |
| RoHS ステータス | Compliant | Compliant |
| Design Software | Intel Quartus Prime (MAX 10 device support) | — |
| Family | — | MAX 10 |
| Memory Bits | — | 387072 bits |
| Embedded Memory (M9K Blocks) | — | [DATA_NEEDED: M9K block count] |
| Multipliers (18x18) | — | 56 |
| Process Technology | — | 55 nm |
| Core Supply Voltage | — | 1.2 V |
| User I/O Banks | — | [DATA_NEEDED: user I/O count] |
| パッケージ | — | 81-UFBGA, WLCSP |
| Package Code | — | V81 |
| On-chip Configuration Flash | — | Yes (dual-configuration) |
| Integrated ADC | — | Yes (12-bit SAR, hardened) |
| PLLs | — | [DATA_NEEDED: PLL count] |
| Lead Free | — | Yes |