5M1270ZT144C5N vs 5M240ZT144I5N 比較
詳細な並列比較: 5M1270ZT144C5N メーカー: Altera および 5M240ZT144I5N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
5M1270ZT144C5N - MAX V CPLD 980 Macrocells 114 I/O TQFP-144 | Intel / Altera
5M1270ZT144C5N ✓ 生産中仕様比較
| パラメータ | 5M1270ZT144C5N | 5M240ZT144I5N |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $12.45 | $13.80 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Series | MAX V | — |
| Logic Elements | 1270 | — |
| Macrocells | 980 | — |
| User I/Os | 114 | — |
| Maximum Internal Frequency | 118.3 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 6.2 ns | — |
| Internal Frequency (typical) | 201 MHz | — |
| User Flash Memory (UFM) | 8 Kbits | 8 Kbits |
| Configuration Memory | Flash (non-volatile, in-system programmable) | Non-volatile (flash) |
| VCCINT (Core Supply) | 1.71 V to 1.89 V | — |
| VCCIO (I/O Supply, per bank) | 1.2 V to 3.3 V | — |
| Number of I/O Banks | 4 | — |
| Supported I/O Standards | LVCMOS, LVTTL, PCI up to 3.3 V, 1.2 V to 3.3 V LVCMOS on JTAG pins | — |
| JTAG Interface | IEEE 1149.1 (TMS, TDI, TDO, TCK in Bank 1) | — |
| Programming Interface | JTAG in-system programmable (Altera Quartus II) | JTAG (IEEE 1149.1) |
| Program/Erase Cycles | Up to 100,000 | — |
| パッケージ | TQFP-144 (22 x 22 mm, 0.5 mm pitch) | TQFP-144 (T144) 22x22 mm |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度 | 0 C to +85 C (commercial grade) | -40 C to +100 C (industrial) |
| RoHS ステータス | Compliant | Compliant |
| Family | — | MAX V |
| Device Logic Elements | — | 240 LE |
| Number of Logic Array Blocks | — | 12 LAB |
| Maximum User I/O Pins | — | 114 |
| Internal Core Voltage | — | 1.8 V |
| I/O Bank Voltage | — | 1.2 V to 3.3 V (multi-voltage) |
| Speed Grade | — | I5 (industrial, -40 C to +100 C) |
| Standby Current (typical) | — | <1 mA |