5M1270ZT144C5N vs 5M240ZT144I5N 비교
다음의 상세 나란히 비교: 5M1270ZT144C5N 제조: Altera 및 5M240ZT144I5N 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
5M1270ZT144C5N - MAX V CPLD 980 Macrocells 114 I/O TQFP-144 | Intel / Altera
5M1270ZT144C5N ✓ 활성사양 비교
| 파라미터 | 5M1270ZT144C5N | 5M240ZT144I5N |
|---|---|---|
| 브랜드 | Altera | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | 활성 | 활성 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $12.45 | $13.80 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Series | MAX V | — |
| Logic Elements | 1270 | — |
| Macrocells | 980 | — |
| User I/Os | 114 | — |
| Maximum Internal Frequency | 118.3 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 6.2 ns | — |
| Internal Frequency (typical) | 201 MHz | — |
| User Flash Memory (UFM) | 8 Kbits | 8 Kbits |
| Configuration Memory | Flash (non-volatile, in-system programmable) | Non-volatile (flash) |
| VCCINT (Core Supply) | 1.71 V to 1.89 V | — |
| VCCIO (I/O Supply, per bank) | 1.2 V to 3.3 V | — |
| Number of I/O Banks | 4 | — |
| Supported I/O Standards | LVCMOS, LVTTL, PCI up to 3.3 V, 1.2 V to 3.3 V LVCMOS on JTAG pins | — |
| JTAG Interface | IEEE 1149.1 (TMS, TDI, TDO, TCK in Bank 1) | — |
| Programming Interface | JTAG in-system programmable (Altera Quartus II) | JTAG (IEEE 1149.1) |
| Program/Erase Cycles | Up to 100,000 | — |
| 패키지 | TQFP-144 (22 x 22 mm, 0.5 mm pitch) | TQFP-144 (T144) 22x22 mm |
| 실장 유형 | Surface Mount | Surface Mount |
| 동작 온도 | 0 C to +85 C (commercial grade) | -40 C to +100 C (industrial) |
| RoHS 상태 | Compliant | Compliant |
| Family | — | MAX V |
| Device Logic Elements | — | 240 LE |
| Number of Logic Array Blocks | — | 12 LAB |
| Maximum User I/O Pins | — | 114 |
| Internal Core Voltage | — | 1.8 V |
| I/O Bank Voltage | — | 1.2 V to 3.3 V (multi-voltage) |
| Speed Grade | — | I5 (industrial, -40 C to +100 C) |
| Standby Current (typical) | — | <1 mA |