5M80ZT100I5N vs 5M240ZT100I5N 比較
詳細な並列比較: 5M80ZT100I5N メーカー: Intel および 5M240ZT100I5N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | 5M80ZT100I5N | 5M240ZT100I5N |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $7.37 | $4.81 |
| Family | MAX V CPLD | MAX V |
| Logic Elements (LE) | 80 | — |
| Macrocells (approx.) | 160 | — |
| User I/O Pins | 64 | — |
| パッケージ | TQFP-100 (100 pins, 0.5 mm pitch) | — |
| Pin-to-Pin Logic Delay (tPD) | 7.5 ns | — |
| Core Supply Voltage (VCCINT) | 1.71 V to 1.89 V (1.8 V typical) | — |
| I/O Supply Voltage (VCCIO) | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Operating Temperature (Industrial) | -40 °C to +100 °C | — |
| Configuration Memory | Internal non-volatile flash (instant-on) | Non-volatile flash (instant-on) |
| UFM (User Flash Memory) | Up to 8 Kbits user-accessible | — |
| JTAG / ISP | IEEE 1149.1 boundary-scan + in-system programming | — |
| 実装タイプ | Surface Mount | Surface Mount |
| MSLレベル | MSL3 (per JEDEC J-STD-020) | [DATA_NEEDED: MSL Level] |
| RoHS ステータス | Compliant | — |
| Series | — | 5M240Z |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Elements | — | 240 |
| Macrocells | — | 192 |
| User Flash Memory | — | 8 Kbit |
| Maximum User I/O | — | 114 |
| User I/O Pins (per datasheet) | — | 79 |
| ピン数 | — | 100 |
| Package Type | — | TQFP-100 (T100) |
| Package Body Size | — | 14 x 14 mm |
| Lead Pitch | — | 0.50 mm |
| Core Voltage (VCCINT) | — | 1.8 V |
| I/O Bank Voltage (VCCIO) | — | 1.2 V to 3.3 V (bank-dependent) |
| Speed Grade | — | -5 |
| Maximum Internal Frequency | — | 118.3 MHz |
| Pin-to-Pin Delay (tPD1) | — | 7.5 ns (per datasheet header) |
| 動作温度 | — | -40 C to +100 C (Industrial) |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP |
| Lead-Free / RoHS | — | Yes (LEAD FREE per datasheet header) |
| AEC-Q100 Automotive | — | Not qualified (Industrial grade) |