EP1810GC-35AB vs EP1810JC-35 比較
詳細な並列比較: EP1810GC-35AB メーカー: Altera および EP1810JC-35 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1810GC-35AB | EP1810JC-35 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.95 | $5.48 |
| Product Family | Classic EPLD | — |
| Technology | CMOS EPROM | — |
| Number of Macrocells | 48 | 48 |
| Number of Usable Gates | 1200 | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Number of I/O Pins | 48 | — |
| Dedicated Input Pins | 12 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Toggle Frequency | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Package Type | Pin Grid Array (PGA), ceramic | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) |
| 動作温度 | [DATA_NEEDED: operating temperature range] | — |
| Programming Method | UV-erasable EPROM, in-system via JTAG-like interface | — |
| RoHS ステータス | unknown | Compliant (per Altera listing) |
| Device Family | — | Classic EPLD (EP1810) |
| Device Type | — | UV-Erasable Complex PLD (UV PLD / CPLD) |
| Propagation Delay (tpd) | — | 35 ns (max) |
| 最大クロック周波数 | — | [DATA_NEEDED: fmax for this speed grade] |
| Process Technology | — | CMOS |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| Maximum Supply Voltage | — | 5.25 V (per distributor listing) |
| Number of Terminals | — | 68 |
| Terminal Form | — | J-Bend |
| 動作温度範囲 | — | 0°C to 70°C (Commercial) |
| Temperature Grade | — | Commercial |
| Erasure Method | — | UV (quartz-windowed ceramic package) |
| Lead-Free Status | — | Lead-free (per distributor listing) |
| 実装タイプ | — | Surface Mount (J-Lead) |
| Logic Architecture | — | Programmable AND/OR array with macrocell outputs |