EP1810GC-35AB vs EP1810JC-35 Comparison

Detailed side-by-side comparison of EP1810GC-35AB by Altera and EP1810JC-35 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP1810GC-35AB EP1810JC-35
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.95 $5.48
Product Family Classic EPLD —
Technology CMOS EPROM —
Number of Macrocells 48 48
Number of Usable Gates 1200 —
Maximum Inputs 64 —
Maximum Outputs 48 —
Number of I/O Pins 48 —
Dedicated Input Pins 12 —
Propagation Delay (tPD) 35 ns —
Maximum Toggle Frequency 62.5 MHz —
Supply Voltage (VCC) 5 V —
Package Type Pin Grid Array (PGA), ceramic CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ)
Operating Temperature [DATA_NEEDED: operating temperature range] —
Programming Method UV-erasable EPROM, in-system via JTAG-like interface —
RoHS Status unknown Compliant (per Altera listing)
Device Family — Classic EPLD (EP1810)
Device Type — UV-Erasable Complex PLD (UV PLD / CPLD)
Propagation Delay (tpd) — 35 ns (max)
Maximum Clock Frequency — [DATA_NEEDED: fmax for this speed grade]
Process Technology — CMOS
Supply Voltage (Vcc) — 5 V (nominal)
Maximum Supply Voltage — 5.25 V (per distributor listing)
Number of Terminals — 68
Terminal Form — J-Bend
Operating Temperature Range — 0°C to 70°C (Commercial)
Temperature Grade — Commercial
Erasure Method — UV (quartz-windowed ceramic package)
Lead-Free Status — Lead-free (per distributor listing)
Mounting Type — Surface Mount (J-Lead)
Logic Architecture — Programmable AND/OR array with macrocell outputs

Datasheets & Resources

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