EP1810JM-45 vs EP1810JC-35 比較
詳細な並列比較: EP1810JM-45 メーカー: Altera および EP1810JC-35 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1810JM-45 | EP1810JC-35 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $14.20 | $5.48 |
| Device Family | Classic EPLD (EP1810 series) | Classic EPLD (EP1810) |
| Macrocells | 48 | — |
| Usable Gates | ~900 gates | — |
| Propagation Delay (tpd) | 45 ns (max, -45 speed grade) | 35 ns (max) |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Technology | CMOS, UV-EPROM configuration | — |
| Package Type | JLCC-68 (ceramic J-leaded chip carrier) | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) |
| Package Code | JM (windowed ceramic, UV-erasable) | — |
| ピン数 | 68 | — |
| 動作温度 | -55 C to +125 C (military grade) | — |
| I/O Compatibility | CMOS / TTL | — |
| Configuration Method | JEDEC fuse map, EPROM programmer | — |
| Programming Technology | UV-erasable EPROM (non-volatile, instant-on) | — |
| 実装タイプ | Surface Mount (J-lead) | Surface Mount (J-Lead) |
| Logic Type | EPLD / PLD (programmable logic device) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status - legacy mil-spec part] | Compliant (per Altera listing) |
| MSLレベル | [DATA_NEEDED: MSL level] | — |
| Device Type | — | UV-Erasable Complex PLD (UV PLD / CPLD) |
| Number of Macrocells | — | 48 |
| 最大クロック周波数 | — | [DATA_NEEDED: fmax for this speed grade] |
| Process Technology | — | CMOS |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| Maximum Supply Voltage | — | 5.25 V (per distributor listing) |
| Number of Terminals | — | 68 |
| Terminal Form | — | J-Bend |
| 動作温度範囲 | — | 0°C to 70°C (Commercial) |
| Temperature Grade | — | Commercial |
| Erasure Method | — | UV (quartz-windowed ceramic package) |
| Lead-Free Status | — | Lead-free (per distributor listing) |
| Logic Architecture | — | Programmable AND/OR array with macrocell outputs |