EP1810JM-45 vs EP1810JC-35 Comparação
Comparação detalhada lado a lado de EP1810JM-45 por Altera e EP1810JC-35 por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP1810JM-45 | EP1810JC-35 |
|---|---|---|
| Marca | Altera | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $14,20 | $5,48 |
| Device Family | Classic EPLD (EP1810 series) | Classic EPLD (EP1810) |
| Macrocells | 48 | — |
| Usable Gates | ~900 gates | — |
| Propagation Delay (tpd) | 45 ns (max, -45 speed grade) | 35 ns (max) |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Technology | CMOS, UV-EPROM configuration | — |
| Package Type | JLCC-68 (ceramic J-leaded chip carrier) | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) |
| Package Code | JM (windowed ceramic, UV-erasable) | — |
| Contagem de pinos | 68 | — |
| Temperatura de operação | -55 C to +125 C (military grade) | — |
| I/O Compatibility | CMOS / TTL | — |
| Configuration Method | JEDEC fuse map, EPROM programmer | — |
| Programming Technology | UV-erasable EPROM (non-volatile, instant-on) | — |
| Tipo de montagem | Surface Mount (J-lead) | Surface Mount (J-Lead) |
| Logic Type | EPLD / PLD (programmable logic device) | — |
| Status RoHS | [DATA_NEEDED: RoHS status - legacy mil-spec part] | Compliant (per Altera listing) |
| Nível MSL | [DATA_NEEDED: MSL level] | — |
| Device Type | — | UV-Erasable Complex PLD (UV PLD / CPLD) |
| Number of Macrocells | — | 48 |
| Frequência máxima de clock | — | [DATA_NEEDED: fmax for this speed grade] |
| Process Technology | — | CMOS |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| Maximum Supply Voltage | — | 5.25 V (per distributor listing) |
| Number of Terminals | — | 68 |
| Terminal Form | — | J-Bend |
| Faixa de temperatura de operação | — | 0°C to 70°C (Commercial) |
| Temperature Grade | — | Commercial |
| Erasure Method | — | UV (quartz-windowed ceramic package) |
| Lead-Free Status | — | Lead-free (per distributor listing) |
| Logic Architecture | — | Programmable AND/OR array with macrocell outputs |