EP1C12Q240I7 vs EP1C12Q240I8ES 比較
詳細な並列比較: EP1C12Q240I7 メーカー: Altera および EP1C12Q240I8ES メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1C12Q240I7 | EP1C12Q240I8ES |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $30.10 | $7.15 |
| Family | Cyclone | — |
| Logic Elements (LE) | 12,060 | — |
| Logic Array Blocks (LABs) | 1,206 | — |
| Total RAM Bits | 239,616 | — |
| User I/O Pins | 173 | — |
| PLLs | 2 | — |
| Process Technology | 130 nm CMOS, 1.5 V core | — |
| パッケージ | 240-pin PQFP / BFQFP (240QFP) | — |
| 実装タイプ | Surface Mount | — |
| 動作温度 | -40°C to +100°C (industrial) | — |
| Speed Grade | I7 | 8 |
| Configuration Method | Serial or parallel, SRAM-based | — |
| Design Software | Altera Quartus II | — |
| MSLレベル | [DATA_NEEDED: MSL Level] | — |
| RoHS ステータス | [DATA_NEEDED: RoHS Status] | unknown |
| Manufacturer | — | Intel |
| Manufacturer Part Number | — | EP1C12Q240I8ES |
| FPGA Family | — | Cyclone |
| Programmable Logic Type | — | FPGA (field-programmable gate array) |
| Configuration Type | — | SRAM-based |
| FPGA Process | — | 1.5-V, 0.13-um, all-layer copper SRAM process |
| Maximum Family Logic Elements | — | 20,060 LEs |
| Maximum Family Embedded RAM | — | 288 Kbits |
| EP1C12 Delivered Logic Elements | — | [DATA_NEEDED: EP1C12 exact LE count] |
| Package Code | — | FQFP |
| Package Description | — | 240-pin square QFP (PQFP/FQFP) |
| Number of Terminals | — | 240 |
| Terminal Form | — | GULL WING |
| Package Shape | — | Square |
| JESD-609 Code | — | e0 |
| Maximum Supply Voltage | — | 1.575 V |
| Nominal Core Supply Voltage | — | 1.5 V |
| Temperature Grade Code | — | I (industrial) |
| Ordering Code Variant | — | ES (engineering sample) |
| Minimum Operating Temperature | — | [DATA_NEEDED: minimum operating temperature] |
| Maximum Operating Temperature | — | [DATA_NEEDED: maximum operating temperature] |
| Supported Configuration | — | Configuration and JTAG boundary-scan testing supported |