EP1K30QC208-1 vs EP1K30QC208-3N 比較
詳細な並列比較: EP1K30QC208-1 メーカー: Intel および EP1K30QC208-3N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1K30QC208-1 | EP1K30QC208-3N |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $10.85 | $15.90 |
| Device Family | ACEX-1K | — |
| Logic Elements (LEs) | 1,728 | — |
| Equivalent Gates | 30,000 | — |
| Logic Array Blocks (LABs) | 216 | 172 |
| Embedded Memory (EAB) | 24,576 bits | — |
| Maximum User I/O | 147 | 147 |
| Core Supply Voltage (VCCINT) | 2.5 V (2.375 V to 2.625 V) | — |
| パッケージ | 208-BFQFP (Plastic Quad Flat Pack, PQFP208) | 208-BQFP / 208-PQFP |
| Terminal Pitch | 0.500 mm | — |
| 実装タイプ | Surface Mount (gull-wing leads) | Surface Mount |
| 動作温度 | 0 °C to +70 °C (commercial) | Industrial (N suffix) |
| Maximum Operating Frequency | up to 250 MHz (family typical) | — |
| Process Technology | 2.5 V CMOS | 0.18 µm CMOS, SRAM-based LUT |
| Configuration Method | SRAM, in-system reconfigurable (volatile) | — |
| Boundary-Scan Test | JTAG IEEE 1149.1 | — |
| I/O Voltage Support | 2.5 V / 3.3 V (multi-volt I/O) | — |
| Configuration Device Support | EPC2, EPC4, EPC8 Enhanced Configuration Devices | — |
| RoHS ステータス | Compliant (lead-free) | Compliant (lead-free / Pb-free) |
| Family | — | ACEX-1K |
| Logic Elements | — | 1,728 |
| Typical Gates | — | 30,000 |
| Embedded Array Blocks (EABs) | — | 6 (24 Kbits total) |
| Speed Grade | — | -3 (fastest) |
| Core Supply Voltage | — | 2.5 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V (5 V tolerant I/O supported) |
| Configuration Interface | — | Serial / Parallel / JTAG (IEEE 1149.1) |