EP1S10B672C7N vs EP1S10B672C7 比較
詳細な並列比較: EP1S10B672C7N メーカー: Intel および EP1S10B672C7 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1S10B672C7N | EP1S10B672C7 |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $67.90 | $140.00 |
| Manufacturer | Intel / Altera | Intel (formerly Altera) |
| Product Family | Stratix | — |
| Logic Family | CMOS | CMOS |
| Logic Elements/Cells | 10570 cells | — |
| Maximum Internal Clock | 420.17 MHz | — |
| Core Supply Voltage | 1.5 V | — |
| Technology Node | 130 nm | — |
| Package Code | BGA | — |
| Number of Terminals | 672 | — |
| Package Body Size | 35 x 35 mm | — |
| Ball Pitch | 1.27 mm | 1.27 mm |
| Package Shape | Square | — |
| Temperature Grade | Commercial extended, 0 to 85 C | Commercial (C) |
| Terminal Form | Ball | — |
| Configuration/JTAG | JTAG boundary-scan per Stratix family data sheet | — |
| Number of User I/O in 672-BGA | [DATA_NEEDED: user I/O count] | — |
| Total RAM Bits | [DATA_NEEDED: total RAM bits] | — |
| Embedded PLLs | [DATA_NEEDED: PLL count] | — |
| Config Device Compatibility | [DATA_NEEDED: supported configuration devices] | — |
| RoHS | unknown - N suffix may indicate Pb-free, not verified in fetched data | — |
| Series | — | Stratix |
| Logic Elements | — | 10,570 |
| Embedded Memory (Total) | — | 920 Kbits |
| DSP Blocks | — | Yes (DSP multiplier blocks) |
| Maximum User I/O Pins | — | [DATA_NEEDED: maximum user I/O count] |
| Process Technology | — | 0.13 µm CMOS |
| Supply Voltage (Core) | — | 1.5 V |
| Package Type | — | 672-ball FineLine BGA |
| Package Dimensions | — | 35 x 35 mm |
| 動作温度 | — | 0 °C to 85 °C (Commercial) |
| Speed Grade | — | 7 |
| Configuration Method | — | JTAG / EPC serial configuration |
| RoHS ステータス | — | [DATA_NEEDED: RoHS compliance] |
| 実装タイプ | — | Surface Mount |