EP1S10B672C7N vs EP1S10B672C7 对比
详细并排对比 EP1S10B672C7N 出自 Intel 和 EP1S10B672C7 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1S10B672C7N | EP1S10B672C7 |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $67.90 | $140.00 |
| Manufacturer | Intel / Altera | Intel (formerly Altera) |
| Product Family | Stratix | — |
| Logic Family | CMOS | CMOS |
| Logic Elements/Cells | 10570 cells | — |
| Maximum Internal Clock | 420.17 MHz | — |
| Core Supply Voltage | 1.5 V | — |
| Technology Node | 130 nm | — |
| Package Code | BGA | — |
| Number of Terminals | 672 | — |
| Package Body Size | 35 x 35 mm | — |
| Ball Pitch | 1.27 mm | 1.27 mm |
| Package Shape | Square | — |
| Temperature Grade | Commercial extended, 0 to 85 C | Commercial (C) |
| Terminal Form | Ball | — |
| Configuration/JTAG | JTAG boundary-scan per Stratix family data sheet | — |
| Number of User I/O in 672-BGA | [DATA_NEEDED: user I/O count] | — |
| Total RAM Bits | [DATA_NEEDED: total RAM bits] | — |
| Embedded PLLs | [DATA_NEEDED: PLL count] | — |
| Config Device Compatibility | [DATA_NEEDED: supported configuration devices] | — |
| RoHS | unknown - N suffix may indicate Pb-free, not verified in fetched data | — |
| Series | — | Stratix |
| Logic Elements | — | 10,570 |
| Embedded Memory (Total) | — | 920 Kbits |
| DSP Blocks | — | Yes (DSP multiplier blocks) |
| Maximum User I/O Pins | — | [DATA_NEEDED: maximum user I/O count] |
| Process Technology | — | 0.13 µm CMOS |
| Supply Voltage (Core) | — | 1.5 V |
| Package Type | — | 672-ball FineLine BGA |
| Package Dimensions | — | 35 x 35 mm |
| 工作温度 | — | 0 °C to 85 °C (Commercial) |
| Speed Grade | — | 7 |
| Configuration Method | — | JTAG / EPC serial configuration |
| RoHS 状态 | — | [DATA_NEEDED: RoHS compliance] |
| 安装类型 | — | Surface Mount |