EP1SGX25DF672C5 vs EP1SGX25DF67216 比較

詳細な並列比較: EP1SGX25DF672C5 メーカー: Intel および EP1SGX25DF67216 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EP1SGX25DF672C5 EP1SGX25DF67216
ブランド Intel Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 NRND Obsolete
在庫状況 In Stock In Stock
単価(USD) $198.00 $198.00
Manufacturer Intel (formerly Altera) —
Series Stratix GX —
Logic Family CMOS —
Device Type FPGA (Field Programmable Gate Array) —
Logic Elements 25,660 25,660
Embedded Memory Bits 1,944,576 —
User I/Os 455 —
Number of Pins / Terminals 672 —
Package Type FBGA-672 (672-BGA, 33 × 33 mm, 1 mm pitch) —
Package Code BGA, Square —
実装タイプ Surface Mount Surface Mount (BGA)
電源電圧 1.5 V (core) —
Speed Grade C5 —
動作温度 0 °C to +85 °C (Commercial) Industrial, -40C to +100C (I-suffix family)
Lead Free / RoHS Lead Free, RoHS compliant —
Embedded Transceivers Up to 20 channels (3.125 Gbps) —
Family — Stratix GX
Total RAM Bits — 1,944,576
Embedded Multipliers (18x18) — [DATA_NEEDED: 18x18 multiplier count]
Number of PLLs — 4
Number of Transceiver Channels — 8 (4 in each of 2 banks)
Max Transceiver Data Rate — 3.1875 Gbps per channel
Min Transceiver Data Rate — 500 Mbps
Core Supply Voltage — 1.5 V
Auxiliary Supply Voltage — 3.3 V
I/O Supply Voltage — 1.5 V / 1.8 V / 2.5 V / 3.3 V (per bank)
Maximum User I/O Pins — [DATA_NEEDED: user I/O count for DF672 package]
パッケージ — 672-ball FineLine BGA (DF672)
On-Die Termination — Yes, 100-ohm differential
Pre-emphasis / Equalization — Programmable (transmitter pre-emphasis; receiver adaptive equalization)
Configuration Schemes — Passive serial, fast passive parallel, JTAG, Altera enhanced configuration
RoHS ステータス — Lead-free / RoHS compliant (per Altera product family documentation)

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