EP1SGX25DF672C5 vs EP1SGX25DF67216 비교
다음의 상세 나란히 비교: EP1SGX25DF672C5 제조: Intel 및 EP1SGX25DF67216 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP1SGX25DF672C5 | EP1SGX25DF67216 |
|---|---|---|
| 브랜드 | Intel | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | NRND | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $198.00 | $198.00 |
| Manufacturer | Intel (formerly Altera) | — |
| Series | Stratix GX | — |
| Logic Family | CMOS | — |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| Logic Elements | 25,660 | 25,660 |
| Embedded Memory Bits | 1,944,576 | — |
| User I/Os | 455 | — |
| Number of Pins / Terminals | 672 | — |
| Package Type | FBGA-672 (672-BGA, 33 × 33 mm, 1 mm pitch) | — |
| Package Code | BGA, Square | — |
| 실장 유형 | Surface Mount | Surface Mount (BGA) |
| 공급 전압 | 1.5 V (core) | — |
| Speed Grade | C5 | — |
| 동작 온도 | 0 °C to +85 °C (Commercial) | Industrial, -40C to +100C (I-suffix family) |
| Lead Free / RoHS | Lead Free, RoHS compliant | — |
| Embedded Transceivers | Up to 20 channels (3.125 Gbps) | — |
| Family | — | Stratix GX |
| Total RAM Bits | — | 1,944,576 |
| Embedded Multipliers (18x18) | — | [DATA_NEEDED: 18x18 multiplier count] |
| Number of PLLs | — | 4 |
| Number of Transceiver Channels | — | 8 (4 in each of 2 banks) |
| Max Transceiver Data Rate | — | 3.1875 Gbps per channel |
| Min Transceiver Data Rate | — | 500 Mbps |
| Core Supply Voltage | — | 1.5 V |
| Auxiliary Supply Voltage | — | 3.3 V |
| I/O Supply Voltage | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (per bank) |
| Maximum User I/O Pins | — | [DATA_NEEDED: user I/O count for DF672 package] |
| 패키지 | — | 672-ball FineLine BGA (DF672) |
| On-Die Termination | — | Yes, 100-ohm differential |
| Pre-emphasis / Equalization | — | Programmable (transmitter pre-emphasis; receiver adaptive equalization) |
| Configuration Schemes | — | Passive serial, fast passive parallel, JTAG, Altera enhanced configuration |
| RoHS 상태 | — | Lead-free / RoHS compliant (per Altera product family documentation) |