EP1SGX25FF1020C5L vs EP1SGX25FF1020C5 比較
詳細な並列比較: EP1SGX25FF1020C5L メーカー: Altera および EP1SGX25FF1020C5 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1SGX25FF1020C5L | EP1SGX25FF1020C5 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $105.00 | $171.00 |
| Family | Stratix GX | Stratix GX |
| Logic Elements | 25,660 cells | 25,660 |
| Process Technology | 130 nm CMOS | 130 nm |
| Package Type | FC-FBGA (Flip-Chip Fine-pitch Ball Grid Array) | FC-FBGA-1020 (33 x 33 mm, 1 mm pitch) |
| ピン数 | 1020 balls | — |
| Core Voltage | 1.5 V | — |
| Speed Grade | C5 (slowest tier) | C5 |
| Maximum Transceiver Data Rate | 3.125 Gbps | — |
| Maximum Operating Frequency | 5000 MHz (internal reference) | — |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度 | [DATA_NEEDED: operating temperature range] | 0 C to 85 C (commercial) |
| Memory Architecture | TriMatrix (M512/M4K/M-RAM blocks) | — |
| I/O Standards Supported | LVDS, LVTTL, LVCMOS, HSTL, SSTL | — |
| Configuration Scheme | Active serial (EPCS), passive serial, JTAG | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | Compliant |
| Series | — | Stratix |
| LABs/CLBs | — | 2,566 |
| Total Memory Bits | — | 1,694,720 bits (1.69 Mbit) |
| Number of I/O | — | 607 |
| Supply Voltage (Core) | — | 1.5 V |
| Multi-Gigabit Transceivers | — | [DATA_NEEDED: MGT count for FF1020 package variant] |
| Embedded PLLs | — | 6 |
| Embedded Multipliers (DSP blocks) | — | [DATA_NEEDED: DSP block count] |
| Logic Family | — | CMOS |
| Lead Free | — | Yes |
| Configuration Modes | — | PS, PPS, FPP, JTAG |
| Design Tool | — | Quartus II / Quartus Prime |