EP1SGX25FF1020C5L vs EP1SGX25FF1020C5 对比

详细并排对比 EP1SGX25FF1020C5L 出自 Altera 和 EP1SGX25FF1020C5 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1SGX25FF1020C5L EP1SGX25FF1020C5
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $105.00 $171.00
Family Stratix GX Stratix GX
Logic Elements 25,660 cells 25,660
Process Technology 130 nm CMOS 130 nm
Package Type FC-FBGA (Flip-Chip Fine-pitch Ball Grid Array) FC-FBGA-1020 (33 x 33 mm, 1 mm pitch)
引脚数量 1020 balls —
Core Voltage 1.5 V —
Speed Grade C5 (slowest tier) C5
Maximum Transceiver Data Rate 3.125 Gbps —
Maximum Operating Frequency 5000 MHz (internal reference) —
安装类型 Surface Mount Surface Mount
工作温度 [DATA_NEEDED: operating temperature range] 0 C to 85 C (commercial)
Memory Architecture TriMatrix (M512/M4K/M-RAM blocks) —
I/O Standards Supported LVDS, LVTTL, LVCMOS, HSTL, SSTL —
Configuration Scheme Active serial (EPCS), passive serial, JTAG —
DSP Blocks [DATA_NEEDED: DSP block count] —
RoHS 状态 [DATA_NEEDED: RoHS compliance] Compliant
Series — Stratix
LABs/CLBs — 2,566
Total Memory Bits — 1,694,720 bits (1.69 Mbit)
Number of I/O — 607
Supply Voltage (Core) — 1.5 V
Multi-Gigabit Transceivers — [DATA_NEEDED: MGT count for FF1020 package variant]
Embedded PLLs — 6
Embedded Multipliers (DSP blocks) — [DATA_NEEDED: DSP block count]
Logic Family — CMOS
Lead Free — Yes
Configuration Modes — PS, PPS, FPP, JTAG
Design Tool — Quartus II / Quartus Prime

数据手册与资源

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