EP1SGX25FF1020C7 vs EP1SGX25FF1020 比較
詳細な並列比較: EP1SGX25FF1020C7 メーカー: Altera および EP1SGX25FF1020 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EP1SGX25FF1020C7 - 25K LE Stratix GX FPGA, 607 I/O, 1020-FBGA | Altera
EP1SGX25FF1020C7 Obsolete仕様比較
| パラメータ | EP1SGX25FF1020C7 | EP1SGX25FF1020 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $1,280.00 | $295.00 |
| Family | Stratix GX | Stratix GX |
| Logic Elements | 25,660 | — |
| Number of LABs/CLBs | 2,566 | — |
| Total RAM Bits | 1,944,576 | — |
| User I/O Count | 607 | — |
| Number of Gates | [DATA_NEEDED: gate count not provided in source data] | — |
| Supply Voltage - Core | 1.425 V to 1.575 V | — |
| 実装タイプ | Surface Mount | Surface Mount (BGA) |
| パッケージ / ケース | 1020-BBGA, FCBGA (33 x 33 mm, 1 mm pitch) | — |
| Supplier Device Package | 1020-FBGA (33x33) | — |
| Logic Family | CMOS | — |
| 動作温度 | 0 C to 85 C | -40C to +85C (industrial variant) / 0C to +85C (commercial variant) |
| Lead Free | Yes (per digchip datasheet) | — |
| RoHS ステータス | [DATA_NEEDED: not stated in source data] | [DATA_NEEDED: RoHS compliance status] |
| Max Operating Frequency (cited) | 4385.97 MHz (per Arrow listing) | — |
| Process Technology | 1.5 V CMOS | 130 nm CMOS |
| Logic Elements (LE) | — | 25,660 |
| Configurable Logic Blocks (CLB) | — | 2,566 |
| Embedded Memory (bits) | — | 1,944,576 |
| Logic Cells (per FPGAkey) | — | 25,660 |
| Combinatorial Delay (Tpd) | — | 7.49 ns (per Microchip USA datasheet summary) |
| Operating Frequency (max) | — | [DATA_NEEDED: max internal operating frequency] |
| パッケージ | — | 1020-ball FCBGA (PBGA, 1.00 mm pitch) |
| Pin/Package Count | — | 1020 |
| 電源電圧 | — | [DATA_NEEDED: core VCC voltage] |
| Serial Transceivers | — | Embedded SERDES (multi-gigabit, protocol-dependent) |
| DSP Blocks | — | Embedded dedicated multipliers |
| PLL / Clock Management | — | Embedded PLLs |
| Configuration Method | — | SRAM-based, configuration via JTAG / passive serial / fast passive parallel |