EP1SGX40DF1020C5ES vs EP1SGX40FF1020C5 比較

詳細な並列比較: EP1SGX40DF1020C5ES メーカー: Intel および EP1SGX40FF1020C5 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

Intel
EP1SGX40DF1020C5ES EP1SGX40DF1020C5ES - 41,250-Cell Stratix GX FPGA | Intel

EP1SGX40DF1020C5ES - 41,250-Cell Stratix GX FPGA | Intel

EP1SGX40DF1020C5ES ✓ 生産中

仕様比較

パラメータ EP1SGX40DF1020C5ES EP1SGX40FF1020C5
ブランド Intel Intel
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 有効 NRND
在庫状況 In Stock In Stock
単価(USD) $0.00 $1,245.00
Product Type Field-Programmable Gate Array (FPGA) —
Logic Family Stratix GX —
Logic Technology CMOS —
Process Technology 130 nm CMOS, 0.13 um
Logic Cells 41,250 cells —
Logic Array Blocks 4,125 LABs —
Configurable I/O Connections 624 input and 624 output connections —
電源電圧 1.5 V —
Reported Maximum Frequency 5,000 MHz —
Reported Maximum CLB Combinatorial Delay 7.49 ns —
Alternative Listed Maximum Clock Frequency 6 MHz —
Terminal Count 1,020 pins —
Package Type FC-FBGA-1020 —
Package Dimensions 33 mm x 33 mm —
Ball Pitch 1 mm —
動作温度 0 C to 85 C 0C to +85C (commercial, -C5 speed grade)
Mounting Configuration Surface-mount ball grid array —
Terminal Form Ball —
Package Code BGA —
Configuration Method [DATA_NEEDED: configuration method] —
RoHS ステータス unknown [DATA_NEEDED: RoHS status]
REACH Status unknown —
AEC-Q100 Qualification unknown —
Family — Stratix GX
Logic Elements — 41,250
Configurable Logic Blocks (CLBs) — 4,125
Total RAM Bits — 3,423,744 bits
Number of I/O Banks — [DATA_NEEDED: number of I/O banks]
Transceiver Channels — 20 (up to 3.125 Gbps)
Core Voltage — 1.5 V (1.425 V to 1.575 V)
パッケージ — 1020-ball FCBGA (FF), 1.00 mm pitch, 33 x 33 mm
Seated Height — 3.50 mm
Maximum User I/O — [DATA_NEEDED: max user I/O count]
DSP Blocks — [DATA_NEEDED: DSP block count]
PLLs — [DATA_NEEDED: PLL count]
実装タイプ — Surface Mount
MSLレベル — [DATA_NEEDED: MSL rating]

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