EP20K200CB652C7ES vs EP20K200EBC652-2X 比較
詳細な並列比較: EP20K200CB652C7ES メーカー: Altera および EP20K200EBC652-2X メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP20K200CB652C7ES | EP20K200EBC652-2X |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | ラストバイ | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $275.00 | $195.00 |
| Family | APEX 20K | APEX-20KE |
| Logic Elements | 8,320 | — |
| Embedded System Block (ESB) RAM | 106,496 bits | — |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count for 652-BGA] | — |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| Speed Grade | -7 | — |
| Operating Temperature (Commercial) | 0 °C to +85 °C | — |
| パッケージ | 652-BGA | 652-BGA |
| 実装タイプ | Surface Mount | Surface Mount |
| Configuration Method | SRAM (volatile, requires external PROM on power-up) | Serial or Parallel PROM, JTAG (IEEE 1149.1) |
| PLL Count | Up to 8 | — |
| Supported I/O Standards | LVTTL, LVCMOS, PCI, GTL+, SSTL, LVDS | — |
| JTAG (IEEE 1149.1) | Yes (boundary-scan) | — |
| Configuration Device Compatibility | EPC2, EPC8, EPC16, EPC64, microprocessor | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | — |
| MSLレベル | [DATA_NEEDED: moisture sensitivity level] | — |
| Series | — | APEX-20KE® |
| Device Logic Elements | — | 8,320 |
| Number of LABs/CLBs | — | 832 |
| Total RAM Bits | — | 106,496 |
| Number of I/O Pins | — | 376 |
| Number of Gates | — | 200,000 (typical) |
| Core Supply Voltage | — | 1.71 V to 1.89 V (1.8 V nominal) |
| Operating Temperature (TJ) | — | 0C to +85C |
| Process Technology | — | 0.18 um CMOS |
| I/O Standard Support | — | LVTTL, LVCMOS, LVDS, PCI, GTL+, SSTL |
| Lead-Free / RoHS | — | Compliant (per DigiKey listing) |