EP20K200EBC356-1 vs EP20K200EBC356-1N 比較
詳細な並列比較: EP20K200EBC356-1 メーカー: Altera および EP20K200EBC356-1N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP20K200EBC356-1 | EP20K200EBC356-1N |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $142.00 | $171.00 |
| Family | APEX 20K (APEX 20KE) | APEX 20KE |
| System Gates | 200,000 | — |
| Logic Elements / Cells | 8,320 | 8,320 |
| Maximum User I/Os | 277 | — |
| Core Voltage | 1.8 V (1.71 V to 1.89 V) | — |
| Process Technology | 0.22 µm CMOS | 0.22 um CMOS |
| Propagation Delay | 2.5 ns | 2.5 ns |
| Internal Performance | Up to 367 MHz | — |
| パッケージ | 356-ball LBGA (35 x 35 mm) | 356-BGA (LBGA, 35 x 35 mm) |
| 実装タイプ | Surface Mount (BGA) | Surface Mount |
| 動作温度 | 0 °C to 85 °C (Commercial) | 0 C to +85 C (commercial) |
| Architecture | MultiCore (LUT + product-term + embedded memory) | — |
| On-chip Memory | Embedded System Blocks (ESB / SRAM) | — |
| Configuration Method | JTAG (ByteBlaster / MasterBlaster), passive serial | SRAM-based, in-system programmable |
| Development Software | Altera Quartus II | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status not stated in verified sources] | [DATA_NEEDED: RoHS status] |
| ライフサイクル状態 | Obsolete / EOL | — |
| Series | — | APEX-20KE |
| Typical Gates | — | 200,000 |
| Number of Macrocells | — | 832 |
| User I/Os | — | 271 |
| Internal Frequency (max) | — | 367 MHz |
| Core Supply Voltage (VCCINT) | — | 1.71 V to 1.89 V (nominal 1.8 V) |
| I/O Supply Voltage | — | MultiVolt 1.8 V / 2.5 V / 3.3 V / 5.0 V |
| MSLレベル | — | 3 (168 hours) |
| Logic Family / Architecture | — | CMOS, MultiCore (LUT + embedded memory) |