EP20K200RC208-2 vs EP20K200RC208-3N 比較
詳細な並列比較: EP20K200RC208-2 メーカー: Altera および EP20K200RC208-3N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EP20K200RC208-3N - APEX 20K FPGA 200K Gates 8320 Cells 167MHz | Altera
EP20K200RC208-3N Obsolete仕様比較
| パラメータ | EP20K200RC208-2 | EP20K200RC208-3N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $79.67 | $39.00 |
| Series | APEX-20K | APEX 20K |
| Family | APEX-20K MultiCore FPGA | APEX-20K |
| Logic Elements (LEs) | 8320 | — |
| System Gates | 200,000 (typical) | 200,000 |
| Embedded Memory (bits) | 106,496 | — |
| Maximum User I/O | 144 | — |
| パッケージ | 208-BQFP / 208-RQFP with Exposed Pad | — |
| ピン数 | 208 | — |
| Speed Grade | -2 (mid-speed, industrial) | — |
| 動作温度 | -40C to +85C (industrial) | — |
| Supply Voltage (Core) | [DATA_NEEDED: core VCC] | — |
| Supply Voltage (I/O) | 3.3 V (multi-standard I/O) | — |
| Configuration Interface | JTAG (IEEE 1149.1) + Altera legacy scheme | — |
| Process Technology | [DATA_NEEDED: process node] | 0.22 um CMOS |
| 実装タイプ | Surface Mount | Surface Mount |
| MSLレベル | [DATA_NEEDED: MSL rating] | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Elements | — | 8320 cells |
| Embedded Memory | — | 106,496 bits |
| Maximum Operating Frequency | — | 167 MHz |
| User I/O Pins | — | 144 |
| Dedicated Inputs | — | 4 |
| Core Supply Voltage | — | 2.5 V |
| I/O Standard Support | — | LVDS, 1.8V APEX-20KE family |
| Package Type | — | 208-RQFP / BFQFP with exposed pad |
| Terminal Pitch | — | 0.5 mm |
| 動作温度範囲 | — | 0C to +85C (industrial) |
| Propagation Delay | — | 3.6 ns |
| Architecture | — | MultiCore (LUT + product-term + embedded memory) |