EP20K200RC208-2 vs EP20K200RC208-3N 对比
详细并排对比 EP20K200RC208-2 出自 Altera 和 EP20K200RC208-3N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EP20K200RC208-3N - APEX 20K FPGA 200K Gates 8320 Cells 167MHz | Altera
EP20K200RC208-3N Obsolete规格对比
| 参数 | EP20K200RC208-2 | EP20K200RC208-3N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $79.67 | $39.00 |
| Series | APEX-20K | APEX 20K |
| Family | APEX-20K MultiCore FPGA | APEX-20K |
| Logic Elements (LEs) | 8320 | — |
| System Gates | 200,000 (typical) | 200,000 |
| Embedded Memory (bits) | 106,496 | — |
| Maximum User I/O | 144 | — |
| 封装 | 208-BQFP / 208-RQFP with Exposed Pad | — |
| 引脚数量 | 208 | — |
| Speed Grade | -2 (mid-speed, industrial) | — |
| 工作温度 | -40C to +85C (industrial) | — |
| Supply Voltage (Core) | [DATA_NEEDED: core VCC] | — |
| Supply Voltage (I/O) | 3.3 V (multi-standard I/O) | — |
| Configuration Interface | JTAG (IEEE 1149.1) + Altera legacy scheme | — |
| Process Technology | [DATA_NEEDED: process node] | 0.22 um CMOS |
| 安装类型 | Surface Mount | Surface Mount |
| MSL 等级 | [DATA_NEEDED: MSL rating] | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Elements | — | 8320 cells |
| Embedded Memory | — | 106,496 bits |
| Maximum Operating Frequency | — | 167 MHz |
| User I/O Pins | — | 144 |
| Dedicated Inputs | — | 4 |
| Core Supply Voltage | — | 2.5 V |
| I/O Standard Support | — | LVDS, 1.8V APEX-20KE family |
| Package Type | — | 208-RQFP / BFQFP with exposed pad |
| Terminal Pitch | — | 0.5 mm |
| 工作温度范围 | — | 0C to +85C (industrial) |
| Propagation Delay | — | 3.6 ns |
| Architecture | — | MultiCore (LUT + product-term + embedded memory) |