EP20K400EBC652-2 vs EP20K400FC784-2 比較
詳細な並列比較: EP20K400EBC652-2 メーカー: Intel および EP20K400FC784-2 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Intel
EP20K400EBC652-2 - APEX-20KE 400K Gates FPGA, 488 I/O | Intel / Altera
EP20K400EBC652-2 Obsolete
仕様比較
| パラメータ | EP20K400EBC652-2 | EP20K400FC784-2 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $60.00 | $175.00 |
| Series | APEX-20KE | — |
| Family | APEX 20K | APEX 20K |
| Logic Elements / Macros | 1664 macros | — |
| Total Gates | 400,000 gates | — |
| User I/Os | 488 | — |
| Total RAM Bits | 212,992 bits | — |
| Core Supply Voltage (VCCINT) | 1.71 V to 1.89 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V | — |
| Propagation Delay | 2.5 ns | — |
| 動作温度 | 0C to 85C | [DATA_NEEDED: exact Tj range] |
| パッケージ | 652-BGA (45x45 mm) | 784-Ball FineLine BGA (FC) |
| Ball Count | 652 | — |
| Architecture | MultiCore (LUT + Embedded System Blocks) | — |
| Logic Family | CMOS | — |
| 実装タイプ | Surface Mount | Surface Mount (BGA) |
| RoHS ステータス | [DATA_NEEDED: rohs status from datasheet] | [DATA_NEEDED: not confirmed in provided data] |
| Device Family Member | — | EP20K400C |
| Typical System Gates | — | 400,000 |
| Maximum User I/O Pins | — | 488 (784-BGA) |
| Logic Elements | — | 16,640 |
| Embedded RAM (ESB) | — | 212 Kbits |
| Maximum Block RAM | — | [DATA_NEEDED: block RAM organization per ESB] |
| Maximum Frequency (internal) | — | [DATA_NEEDED: fmax, datasheet-dependent] |
| Process Technology | — | 0.22 µm CMOS SRAM |
| Core Voltage | — | 2.5 V |
| MultiVolt I/O Voltage | — | 1.8 V / 2.5 V / 3.3 V |
| Supported I/O Standards | — | LVTTL, LVCMOS, PCI, SSTL-2, SSTL-3, GTL+, CTT |
| Configuration Mode | — | Serial / Parallel SRAM-volatile (external PROM required) |
| Speed Grade | — | -2 (industrial) |
| MSLレベル | — | 3 (per Partstack listing) |
| Peak Reflow Temperature | — | 220 °C (per Partstack listing) |
| Hot Socketing | — | Supported |
| JTAG / Boundary-Scan | — | IEEE 1149.1 compliant |