EP20K400GC655-2N vs EP20K400GC655-2V 比較
詳細な並列比較: EP20K400GC655-2N メーカー: Altera および EP20K400GC655-2V メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP20K400GC655-2N | EP20K400GC655-2V |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $127.50 | $92.75 |
| Family | APEX 20KC | APEX 20KC (1.8 V, LVDS) |
| Number of Logic Elements | 16640 | — |
| Number of Logic Cells | 16640 | — |
| Total System Gates | 400000 | — |
| Total RAM Bits | 212992 | 212,992 |
| Number of I/O | [DATA_NEEDED: I/O count] | [DATA_NEEDED: I/O count] |
| Number of LABs/CLBs | [DATA_NEEDED: LAB count] | — |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V | 2.375 V to 2.625 V (nominal 2.5 V) |
| I/O Voltage (VCCIO) | 2.5 V (LVDS-capable) | — |
| Process Technology | 0.22 µm CMOS | CMOS, 0.18 um |
| Maximum Operating Frequency | 200 MHz | — |
| Propagation Delay (Tpd) | 3.1 ns | — |
| パッケージ / ケース | 655-BCPGA (Ceramic Pin Grid Array) | — |
| Supplier Device Package | 655-CPGA, 62.48 x 62.48 mm | — |
| 動作温度 | Industrial (per Altera part-number -N suffix) | [DATA_NEEDED: temperature grade] |
| 実装タイプ | Through-Hole (CPGA, socket-compatible) | Through-hole (CPGA) |
| LVDS Support | Yes | Yes |
| Architecture | MultiCore (LUT + product-term + embedded memory) | MultiCore (LUT + product-term + embedded memory) |
| Configuration Method | JTAG / Passive Serial | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | unknown |
| MSLレベル | [DATA_NEEDED: MSL level] | — |
| Series | — | APEX-20KC |
| Logic Elements | — | 16,640 |
| System Gates | — | ~400,000 (typical marketing figure) |
| Propagation Delay | — | 3.000 ns |
| パッケージ | — | 655-CPGA (62.48 x 62.48 mm) |
| Package Type | — | Ceramic Pin Grid Array, through-hole |
| Speed Grade | — | -2 |
| Lead-Free | — | unknown |