EP20K400GC655-2N vs EP20K400GC655-2V 对比

详细并排对比 EP20K400GC655-2N 出自 Altera 和 EP20K400GC655-2V 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EP20K400GC655-2V EP20K400GC655-2V - 400K Gate APEX-20KC FPGA 655-CPGA | Altera

EP20K400GC655-2V - 400K Gate APEX-20KC FPGA 655-CPGA | Altera

EP20K400GC655-2V ⚠ 最后一次采购

规格对比

参数 EP20K400GC655-2N EP20K400GC655-2V
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $127.50 $92.75
Family APEX 20KC APEX 20KC (1.8 V, LVDS)
Number of Logic Elements 16640 —
Number of Logic Cells 16640 —
Total System Gates 400000 —
Total RAM Bits 212992 212,992
Number of I/O [DATA_NEEDED: I/O count] [DATA_NEEDED: I/O count]
Number of LABs/CLBs [DATA_NEEDED: LAB count] —
Core Voltage (VCCINT) 1.71 V to 1.89 V 2.375 V to 2.625 V (nominal 2.5 V)
I/O Voltage (VCCIO) 2.5 V (LVDS-capable) —
Process Technology 0.22 µm CMOS CMOS, 0.18 um
Maximum Operating Frequency 200 MHz —
Propagation Delay (Tpd) 3.1 ns —
封装 / 外壳 655-BCPGA (Ceramic Pin Grid Array) —
Supplier Device Package 655-CPGA, 62.48 x 62.48 mm —
工作温度 Industrial (per Altera part-number -N suffix) [DATA_NEEDED: temperature grade]
安装类型 Through-Hole (CPGA, socket-compatible) Through-hole (CPGA)
LVDS Support Yes Yes
Architecture MultiCore (LUT + product-term + embedded memory) MultiCore (LUT + product-term + embedded memory)
Configuration Method JTAG / Passive Serial —
RoHS 状态 [DATA_NEEDED: RoHS status] unknown
MSL 等级 [DATA_NEEDED: MSL level] —
Series — APEX-20KC
Logic Elements — 16,640
System Gates — ~400,000 (typical marketing figure)
Propagation Delay — 3.000 ns
封装 — 655-CPGA (62.48 x 62.48 mm)
Package Type — Ceramic Pin Grid Array, through-hole
Speed Grade — -2
Lead-Free — unknown

数据手册与资源

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