EP20K400GI655-1 vs EP20K400GI655-2 比較
詳細な並列比較: EP20K400GI655-1 メーカー: Altera および EP20K400GI655-2 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP20K400GI655-1 | EP20K400GI655-2 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $195.00 | $175.00 |
| Family | APEX 20K | — |
| Device Series | EP20K400 | — |
| Technology | CMOS, SRAM-based | CMOS SRAM |
| Logic Elements | 16640 | — |
| Typical Gates | 400000 | — |
| Maximum User I/O | 502 | 496 |
| Dedicated Inputs | 4 | 6 |
| Total Terminals | 655 | — |
| Propagation Delay | 2.5 ns | 3.1 ns (typical) |
| Package Type | Ceramic Pin Grid Array (CPGA-655) | — |
| JESD-30 Package Code | S-CPGA-P655 | — |
| 動作温度 | -40C to +85C (Industrial) | -40C to +85C (industrial) |
| Moisture Sensitivity Level | MSL 1 | 1 (per Altera family) |
| Peak Reflow Temperature | 220 C | — |
| Programmability | In-system, JTAG boundary-scan (IEEE 1149.1) | — |
| Process Node | 0.18 micrometer CMOS | — |
| RoHS ステータス | Compliant | [DATA_NEEDED: RoHS status] |
| Manufacturer | — | Altera Corporation |
| Series | — | APEX 20K (EP20K400) |
| Device Type | — | Field Programmable Gate Array (FPGA) |
| Typical Gate Count | — | 400,000 gates |
| Logic Elements (LE) | — | 16,640 |
| Number of Terminals | — | 655 |
| パッケージ | — | SPGA-655 (47 mm x 47 mm) |
| Nominal Supply Voltage | — | 2.5 V |
| Supply Voltage Range | — | 2.375 V to 2.625 V |
| 実装タイプ | — | Through-Hole / Socket |
| Configuration Method | — | JTAG, Passive Serial, Passive Parallel |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, GTL+ |
| Embedded Memory | — | Embedded System Blocks (ESBs) |
| ライフサイクル状態 | — | Obsolete (legacy Altera APEX 20K family) |