EP20K600CF672I-8ES vs EP20K600CF672C8N 比較
詳細な並列比較: EP20K600CF672I-8ES メーカー: Altera および EP20K600CF672C8N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EP20K600CF672I-8ES - APEX 20KC 600K-Gate FPGA, 672-BGA | Intel / Altera
EP20K600CF672I-8ES Obsolete
仕様比較
| パラメータ | EP20K600CF672I-8ES | EP20K600CF672C8N |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $119.00 | $108.00 |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements | 24,320 | — |
| Typical Gates | 600,000 (ASIC-equivalent) | — |
| Embedded Memory Bits | 311,296 | — |
| Maximum User I/O Pins | 508 | — |
| Embedded PLLs | 4 | — |
| Core Voltage | 1.8 V | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, SSTL, HSTL, GTL+ | — |
| Process Technology | 0.18 micron CMOS SRAM | — |
| Speed Grade | -8 (slower) | — |
| 動作温度 | -40C to +100C (Industrial) | 0°C to 85°C |
| パッケージ | 672-ball BGA (FineLine BGA, 1.27 mm pitch) | BGA-652, 45 x 45 mm, 1.27 mm pitch |
| Configuration Modes | Passive Serial, Fast Passive Parallel, Passive Parallel Asynchronous, JTAG | — |
| In-System Programmability | Yes (ISP via EPC16, EPC8, EPC4, EPC2, EPC1) | — |
| RoHS ステータス | Non-compliant (legacy Altera leaded BGA process) | unknown |
| MSLレベル | [DATA_NEEDED: moisture sensitivity level] | — |
| Device Type | — | SPLD |
| Product Type | — | FPGA / programmable logic device |
| Nominal Gate Capacity | — | 600K gates |
| Logic Elements or Cells | — | 24,320 |
| Macros | — | 2,432 |
| User I/O Count | — | 508 |
| Package Terminals | — | 652 pins |
| Package Description | — | 672-pin FC-FBGA |
| 電源電圧 | — | 1.8 V |
| Listed Frequency | — | 301.21 MHz |
| Propagation Delay | — | 1.48 ns |
| Fabrication Process | — | 0.15 µm |
| Interconnect Metal | — | All-layer copper metal |
| I/O Configuration | — | 508 user I/O |
| 実装タイプ | — | Surface mount |
| REACH Status | — | unknown |
| AEC-Q100 Qualification | — | unknown |
| Configuration Method | — | [DATA_NEEDED: configuration memory and programming method] |
| Core Current | — | [DATA_NEEDED: core supply current] |
| I/O Bank Voltage | — | [DATA_NEEDED: supported I/O voltage range] |
| Junction Temperature | — | [DATA_NEEDED: maximum junction temperature] |
| 熱抵抗 | — | [DATA_NEEDED: junction-to-ambient thermal resistance] |