EP20K600CF672I8N vs EP20K600CF672C8N 比較
詳細な並列比較: EP20K600CF672I8N メーカー: Intel および EP20K600CF672C8N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP20K600CF672I8N | EP20K600CF672C8N |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $138.00 | $108.00 |
| Device Family | APEX 20KC | — |
| Device Type | SPLD / PLD (FPGA-class) | SPLD |
| System Gates | 600K | — |
| Logic Elements / Cells | 24,320 | — |
| Maximum User I/O (digchip) | 488 | — |
| Maximum User I/O (Altera) | 508 | — |
| Total Package Pins | 672 | — |
| Package Type | FC-FBGA (Fine-pitch Chip-Scale BGA), 45 x 45 mm, 1.27 mm pitch | — |
| Internal Performance | 301.21 MHz | — |
| Propagation Delay | 1.48 ns | 1.48 ns |
| Core Supply Voltage | 1.8 V | — |
| Process Technology | 0.15-um all-layer copper-metal | — |
| 動作温度 | 0C to 85C (Industrial) | 0°C to 85°C |
| Pin-Compatible With | APEX 20KE family | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | unknown |
| Product Type | — | FPGA / programmable logic device |
| Family | — | APEX 20KC |
| Nominal Gate Capacity | — | 600K gates |
| Logic Elements or Cells | — | 24,320 |
| Macros | — | 2,432 |
| User I/O Count | — | 508 |
| Package Terminals | — | 652 pins |
| パッケージ | — | BGA-652, 45 x 45 mm, 1.27 mm pitch |
| Package Description | — | 672-pin FC-FBGA |
| 電源電圧 | — | 1.8 V |
| Listed Frequency | — | 301.21 MHz |
| Fabrication Process | — | 0.15 µm |
| Interconnect Metal | — | All-layer copper metal |
| I/O Configuration | — | 508 user I/O |
| 実装タイプ | — | Surface mount |
| REACH Status | — | unknown |
| AEC-Q100 Qualification | — | unknown |
| Configuration Method | — | [DATA_NEEDED: configuration memory and programming method] |
| Core Current | — | [DATA_NEEDED: core supply current] |
| I/O Bank Voltage | — | [DATA_NEEDED: supported I/O voltage range] |
| Junction Temperature | — | [DATA_NEEDED: maximum junction temperature] |
| 熱抵抗 | — | [DATA_NEEDED: junction-to-ambient thermal resistance] |