EP2A25F672C9 vs EP2A25F672C7 比較
詳細な並列比較: EP2A25F672C9 メーカー: Altera および EP2A25F672C7 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP2A25F672C9 | EP2A25F672C7 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $700.00 | $118.00 |
| Family | APEX II | — |
| Logic Elements (LE) | Approximately 25,000 | — |
| Macro Cells | 2432 | — |
| User I/O | 492 | — |
| パッケージ | 672-ball FCBGA (FineLine BGA) | 672-ball FCBGA (FineLine BGA) |
| Package Dimensions | 27 mm x 27 mm | — |
| Ball Pitch | 1.0 mm | — |
| Process Technology | 0.15 µm all-layer copper, up to 8 metal layers | 0.15-um all-layer copper, up to 8 metal layers |
| Logic Family | CMOS | — |
| Propagation Delay | 1.69 ns | — |
| 動作温度 | 0°C to 85°C (Commercial) | 0C to +85C (Commercial) |
| 電源電圧 | [DATA_NEEDED: core VCC voltage] | — |
| I/O Standards | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL (multi-voltage 1.5/1.8/2.5/3.3 V) | — |
| Configuration | Passive Serial, Passive Parallel Synchronous, JTAG | — |
| Embedded Memory | ESBs for dual-port RAM, ROM, FIFO | — |
| 実装タイプ | Surface Mount | — |
| RoHS ステータス | [DATA_NEEDED] | [DATA_NEEDED: RoHS status] |
| Product Family | — | APEX II |
| Logic Elements | — | 25,000 |
| Maximum System Gates | — | 1,650,000 |
| Maximum RAM Bits | — | 422,976 |
| User I/O Count | — | 492 |
| Supply Voltage (Core) | — | 1.5 V |
| LVDS Data Rate | — | 1 Gbps per channel (True-LVDS) |
| I/O Standards Supported | — | LVDS, LVPECL, PCML, HyperTransport |
| Speed Grade | — | -7 |
| Configuration Mode | — | Passive Serial, Passive Parallel, JTAG |
| Embedded System Blocks (ESB) | — | Yes - RAM, ROM, CAM, multiplier support |