EP2A25F672I8 vs EP2A25F724 比較

詳細な並列比較: EP2A25F672I8 メーカー: Altera および EP2A25F724 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EP2A25F672I8 EP2A25F724
ブランド Altera Altera
カテゴリ FPGA & CPLD Memory ICs
ライフサイクル状態 Obsolete NRND
在庫状況 In Stock In Stock
単価(USD) $125.00 $112.00
Family APEX II —
Logic Elements / Cells 24,320 —
Equivalent Gates 900,000 —
Embedded Memory (RAM bits) 622,592 —
User I/Os 492 —
Number of PLLs 4 —
Process Technology 0.15 µm CMOS, up to 8 metal layers —
Core Supply Voltage 1.5 V —
Propagation Delay 1.69 ns (typical) —
Internal Performance 333 MHz (per legacy datasheet) —
LVDS / High-Speed I/O Yes, up to 1 Gbps —
パッケージ 672-ball FC-FBGA (FineLine BGA), 27 × 27 mm, 1 mm pitch 724-ball FineLine BGA
実装タイプ Surface Mount (BGA) Surface Mount (BGA)
動作温度 –40 °C to +85 °C (industrial, 'I' grade) [DATA_NEEDED: operating temperature grade]
Speed Grade I8 (industrial, 8-speed-grade per APEX II ordering scheme) —
JTAG / Boundary Scan IEEE 1149.1 compliant —
I/O Standards Supported LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, GTL+, PCI —
RoHS ステータス unknown Compliant
Lead-Free Status unknown —
Device Type — Enhanced Configuration Device (EPC)
Target FPGA Family — Altera APEX II (EP2A-series)
Memory Technology — Flash (non-volatile, no battery required)
Configuration Modes — Passive Serial, Passive Parallel Async, Passive Parallel Sync
JTAG Support — IEEE Std. 1149.1 (boundary-scan / ISP)
Multi-Device Configuration — Yes - supports daisy-chained APEX II FPGAs
In-System Programmability — Yes (via JTAG)
電源電圧 — [DATA_NEEDED: VCC nominal]
On-chip Oscillator — Yes (internal configuration clock)
User Flash Region — Yes (separate from configuration data)
ライフサイクル状態 — Not Recommended for New Designs (NRND) - Altera acquired by Intel 2015

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