EP2S30F484I5N vs EP2S60F484I5N 比較
詳細な並列比較: EP2S30F484I5N メーカー: Intel および EP2S60F484I5N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP2S30F484I5N | EP2S60F484I5N |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $171.00 | $1,325.00 |
| Family | Stratix II | Field Programmable Gate Array (FPGA) |
| Logic Elements | 33,880 | — |
| Adaptive Logic Modules (ALMs) | 13,552 | — |
| Maximum Operating Frequency | 609.76 MHz | — |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Core Voltage | 1.2 V | — |
| パッケージ | 484-ball FC-FBGA | 484-ball FC-FBGA (Flip-Chip Fine-pitch BGA), 1.00 mm pitch |
| Number of Pins/Balls | 484 | — |
| Speed Grade | I5 (industrial) | I5 (industrial, slow-speed for low power) |
| Temperature Grade | Industrial (-40C to +100C ambient) | — |
| 実装タイプ | Surface Mount | Surface Mount (BGA) |
| MSLレベル | [DATA_NEEDED: MSL level] | — |
| RoHS ステータス | Compliant | [DATA_NEEDED: rohs status not stated in verified data] |
| Lead-Free | Yes | — |
| Cell Count | 33,880 cells | — |
| Series | — | Stratix II (EP2S60) |
| Logic Elements (LE) | — | 60,440 |
| Adaptive Logic Modules (ALM) | — | 24,176 |
| Embedded Memory (bits) | — | 2,544,192 |
| Embedded Memory (M512/M4K/M-RAM blocks) | — | M512: 330, M4K: 255, M-RAM: 2 |
| DSP Blocks (18-bit multipliers) | — | 48 blocks (192 18x18 multipliers) |
| PLLs | — | 12 (4 enhanced + 8 fast) |
| Maximum User I/O Pins | — | 334 |
| Maximum Fabric Clock | — | 609.76 MHz |
| Core Supply Voltage | — | 1.2 V typical |
| 動作温度範囲 | — | -40 °C to +100 °C (industrial) |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: lead-free / halogen-free status] |
| Configuration Interface | — | JTAG (IEEE 1149.1), Passive Serial, Fast Passive Parallel |
| Design Tool | — | Quartus II (legacy; current Intel Quartus Prime with Stratix II device support) |