EP610DC-20 vs EP610DI-35 比較
詳細な並列比較: EP610DC-20 メーカー: Intel および EP610DI-35 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Intel
EP610DI-35 - 16-Macrocell Classic EPLD, 35ns, 5V, 24-CDIP | Intel / Altera
EP610DI-35 Obsolete仕様比較
| パラメータ | EP610DC-20 | EP610DI-35 |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $15.85 | $9.85 |
| Product Type | CMOS UV-Erasable Programmable Logic Device (EPLD) | — |
| Family | Classic EP610 | Altera Classic EPLD |
| Logic Macrocells | 16 | — |
| Dedicated Inputs | 4 | — |
| I/O Pins | 16 (bidirectional) | 16 bidirectional |
| Total Usable Pins | 20 | — |
| Product Terms (p-terms) | 160 | — |
| Propagation Delay (tPD) | 22 ns | — |
| Maximum Toggle Frequency (fMAX) | 55.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| 動作温度 | 0 °C to 70 °C (commercial) | [DATA_NEEDED: industrial/commercial grade range] |
| パッケージ | 24-pin Ceramic DIP (CDIP-24) with UV window | 24-pin CDIP (Ceramic DIP) |
| Programming Method | UV erasure + parallel programmer | — |
| Process Technology | CMOS, UV-erasable floating gate | — |
| 実装タイプ | Through-hole | Through-hole |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: not confirmed in supplied web data] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Series | — | EP610 |
| Logic Cells / Macrocells | — | 16 macrocells |
| Usable Gates | — | 300 |
| Product Terms | — | 160 |
| Total Inputs | — | 20 (including 4 dedicated inputs) |
| Propagation Delay (tpd) | — | 35 ns |
| Maximum Toggle Frequency | — | 28.6 MHz |
| Internal Pipelined Data Rate | — | Up to 100 MHz |
| 電源電圧 | — | 5 V |
| Technology | — | CMOS, UV-erasable |