EP610DC-20 vs EP610DI-35 对比
详细并排对比 EP610DC-20 出自 Intel 和 EP610DI-35 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Intel
EP610DI-35 - 16-Macrocell Classic EPLD, 35ns, 5V, 24-CDIP | Intel / Altera
EP610DI-35 Obsolete规格对比
| 参数 | EP610DC-20 | EP610DI-35 |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $15.85 | $9.85 |
| Product Type | CMOS UV-Erasable Programmable Logic Device (EPLD) | — |
| Family | Classic EP610 | Altera Classic EPLD |
| Logic Macrocells | 16 | — |
| Dedicated Inputs | 4 | — |
| I/O Pins | 16 (bidirectional) | 16 bidirectional |
| Total Usable Pins | 20 | — |
| Product Terms (p-terms) | 160 | — |
| Propagation Delay (tPD) | 22 ns | — |
| Maximum Toggle Frequency (fMAX) | 55.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| 工作温度 | 0 °C to 70 °C (commercial) | [DATA_NEEDED: industrial/commercial grade range] |
| 封装 | 24-pin Ceramic DIP (CDIP-24) with UV window | 24-pin CDIP (Ceramic DIP) |
| Programming Method | UV erasure + parallel programmer | — |
| Process Technology | CMOS, UV-erasable floating gate | — |
| 安装类型 | Through-hole | Through-hole |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: not confirmed in supplied web data] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Series | — | EP610 |
| Logic Cells / Macrocells | — | 16 macrocells |
| Usable Gates | — | 300 |
| Product Terms | — | 160 |
| Total Inputs | — | 20 (including 4 dedicated inputs) |
| Propagation Delay (tpd) | — | 35 ns |
| Maximum Toggle Frequency | — | 28.6 MHz |
| Internal Pipelined Data Rate | — | Up to 100 MHz |
| 电源电压 | — | 5 V |
| Technology | — | CMOS, UV-erasable |