EP610DC-30 vs EP610DC-20 比較
詳細な並列比較: EP610DC-30 メーカー: Altera および EP610DC-20 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP610DC-30 | EP610DC-20 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $10.40 | $15.85 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | CMOS UV-Erasable Programmable Logic Device (EPLD) |
| Family | EP610 (Classic Device Family) | Classic EP610 |
| Macrocells | 16 | — |
| Logic Expanders | 4 (4 product terms per macrocell) | — |
| Usable Gates | 300 | — |
| Maximum Pipelined Clock Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 30 ns | 22 ns |
| Dedicated Inputs | 16 | 4 |
| I/O Pins | 16 (with output enable) | 16 (bidirectional) |
| パッケージ | 24-pin CERDIP (windowed) | 24-pin Ceramic DIP (CDIP-24) with UV window |
| 実装タイプ | Through-Hole | Through-hole |
| Speed Grade | -30 (30 ns tPD) | — |
| Technology | CMOS EPROM | — |
| Programmability | UV-erasable, windowed EPROM | — |
| Security Bit | Yes (protects design after programming) | — |
| Output Modes | Registered and Combinatorial | — |
| 動作温度 | Commercial (0C to +70C) | 0 °C to 70 °C (commercial) |
| Logic Macrocells | — | 16 |
| Total Usable Pins | — | 20 |
| Product Terms (p-terms) | — | 160 |
| Maximum Toggle Frequency (fMAX) | — | 55.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Programming Method | — | UV erasure + parallel programmer |
| Process Technology | — | CMOS, UV-erasable floating gate |
| RoHS ステータス | — | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |