EP610DI-30 vs EP610DC-35 比較
詳細な並列比較: EP610DI-30 メーカー: Rochester Electronics および EP610DC-35 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Rochester Electronics
EP610DI-30 - 16-Macrocell Classic EPLD, 30ns, CERDIP-24 | Rochester Electronics
EP610DI-30 ✓ 生産中
仕様比較
| パラメータ | EP610DI-30 | EP610DC-35 |
|---|---|---|
| ブランド | Rochester Electronics | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $23.50 | $18.40 |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD - Classic EPLD |
| Family | Classic EP610 | Altera Classic EP610 |
| Macrocells | 16 | 16 |
| Propagation Delay (tPD) | 30 ns | 35 ns |
| Pipelined Data Rate | 100 MHz | up to 100 MHz |
| Technology | CMOS | — |
| 電源電圧 | 5 V (single supply) | — |
| パッケージ | CERDIP-24 (windowed, UV-erasable) | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| 実装タイプ | Through-Hole | Through-Hole (DIP) |
| Programmable Elements | EPROM (UV-erasable, windowed) | — |
| 動作温度 | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| I/O Pins | [DATA_NEEDED: I/O pin count] | — |
| Logic Capacity | [DATA_NEEDED: usable gates / logic capacity] | — |
| RoHS ステータス | unknown | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Lead-Free | unknown | — |
| Original Manufacturer | Altera (now Intel) | — |
| Current Supplier | Rochester Electronics (authorized continuing source) | — |
| MSLレベル | N/A (through-hole, non-surface-mount) | — |
| Usable Gates | — | 300 |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Process Technology | — | CMOS |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |