EP610IDC-15 vs EP610DI-30 比較
詳細な並列比較: EP610IDC-15 メーカー: Intel および EP610DI-30 メーカー: Rochester Electronics。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Rochester Electronics
EP610DI-30 - 16-Macrocell Classic EPLD, 30ns, CERDIP-24 | Rochester Electronics
EP610DI-30 ✓ 生産中仕様比較
| パラメータ | EP610IDC-15 | EP610DI-30 |
|---|---|---|
| ブランド | Intel | Rochester Electronics |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | ラストバイ | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.95 | $23.50 |
| Device Family | Altera Classic EPLD | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 15 ns | 30 ns |
| Maximum Frequency | 66 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| 動作温度 | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Process Technology | CMOS, UV-erasable / OTP | — |
| パッケージ | 24-pin CerDIP (ceramic DIP) | CERDIP-24 (windowed, UV-erasable) |
| 実装タイプ | Through-hole | Through-Hole |
| I/O Pins | 24 (per package; macrocell-programmable) | [DATA_NEEDED: I/O pin count] |
| Logic-Block Architecture | AND/OR macrocell array with programmable flip-flops | — |
| Program/Erase | UV-erasable, OTP-compatible | — |
| Development Tool | MAX+PLUS II | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status of CerDIP variant] | unknown |
| Programming Current | 11.0 mA typical (per Classic family datasheet) | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Classic EP610 |
| Pipelined Data Rate | — | 100 MHz |
| Technology | — | CMOS |
| 電源電圧 | — | 5 V (single supply) |
| Programmable Elements | — | EPROM (UV-erasable, windowed) |
| Logic Capacity | — | [DATA_NEEDED: usable gates / logic capacity] |
| Lead-Free | — | unknown |
| Original Manufacturer | — | Altera (now Intel) |
| Current Supplier | — | Rochester Electronics (authorized continuing source) |
| MSLレベル | — | N/A (through-hole, non-surface-mount) |