EP610IDC-15 vs EP610DI-30 비교
다음의 상세 나란히 비교: EP610IDC-15 제조: Intel 및 EP610DI-30 제조: Rochester Electronics. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Rochester Electronics
EP610DI-30 - 16-Macrocell Classic EPLD, 30ns, CERDIP-24 | Rochester Electronics
EP610DI-30 ✓ 활성사양 비교
| 파라미터 | EP610IDC-15 | EP610DI-30 |
|---|---|---|
| 브랜드 | Intel | Rochester Electronics |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | 최종 구매 | 활성 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.95 | $23.50 |
| Device Family | Altera Classic EPLD | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 15 ns | 30 ns |
| Maximum Frequency | 66 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| 동작 온도 | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Process Technology | CMOS, UV-erasable / OTP | — |
| 패키지 | 24-pin CerDIP (ceramic DIP) | CERDIP-24 (windowed, UV-erasable) |
| 실장 유형 | Through-hole | Through-Hole |
| I/O Pins | 24 (per package; macrocell-programmable) | [DATA_NEEDED: I/O pin count] |
| Logic-Block Architecture | AND/OR macrocell array with programmable flip-flops | — |
| Program/Erase | UV-erasable, OTP-compatible | — |
| Development Tool | MAX+PLUS II | — |
| RoHS 상태 | [DATA_NEEDED: RoHS status of CerDIP variant] | unknown |
| Programming Current | 11.0 mA typical (per Classic family datasheet) | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Classic EP610 |
| Pipelined Data Rate | — | 100 MHz |
| Technology | — | CMOS |
| 공급 전압 | — | 5 V (single supply) |
| Programmable Elements | — | EPROM (UV-erasable, windowed) |
| Logic Capacity | — | [DATA_NEEDED: usable gates / logic capacity] |
| Lead-Free | — | unknown |
| Original Manufacturer | — | Altera (now Intel) |
| Current Supplier | — | Rochester Electronics (authorized continuing source) |
| MSL 레벨 | — | N/A (through-hole, non-surface-mount) |