EP610IPC-25 vs EP610ILC-10 比較
詳細な並列比較: EP610IPC-25 メーカー: Intel および EP610ILC-10 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP610IPC-25 | EP610ILC-10 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $8.85 | $7.20 |
| Family | Classic EPLD (EP610) | — |
| Architecture | PAL-type, CMOS, Erasable | PAL-type with macrocells |
| Propagation Delay (tpd) | 25 ns (max) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Maximum Inputs | 20 | — |
| Maximum I/O Pins | 16 | — |
| Dedicated Outputs | 16 | — |
| Product Terms | 160 | 160 |
| 動作温度 | 0 °C to +70 °C (Commercial) | [DATA_NEEDED: operating temperature range] |
| パッケージ | 24-pin PDIP (Plastic DIP) | PLCC-28 (plastic J-lead chip carrier) |
| Technology | CMOS, UV-erasable (windowless in IPC pkg) | — |
| TTL Compatibility | 100% TTL emulation | — |
| 実装タイプ | Through-Hole | Surface Mount (PLCC socket or solder) |
| MSLレベル | [DATA_NEEDED: MSL level] | — |
| RoHS ステータス | Non-compliant (contains Pb, PDIP package) | [DATA_NEEDED: RoHS compliance] |
| Logic Capacity | Equivalent to ~24 standard 24-pin PALs | — |
| Device Family | — | Classic EPLD |
| Product Type | — | UV-Erasable / OTP PLD |
| Macrocells | — | 16 |
| Usable Gates | — | 300 |
| I/O Pins | — | 16 |
| Dedicated Inputs | — | 4 |
| 電源電圧 | — | 5 V (single supply) |
| Pin-to-Pin Delay (tPD) | — | 10 ns (grade -10) |
| Counter Frequency (fCNT) | — | 100 MHz |
| Logic Family Compatibility | — | TTL (5 V CMOS/TTL-compatible I/O) |