EP610IPC-25 vs EP610ILC-10 对比
详细并排对比 EP610IPC-25 出自 Intel 和 EP610ILC-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP610IPC-25 | EP610ILC-10 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $8.85 | $7.20 |
| Family | Classic EPLD (EP610) | — |
| Architecture | PAL-type, CMOS, Erasable | PAL-type with macrocells |
| Propagation Delay (tpd) | 25 ns (max) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Maximum Inputs | 20 | — |
| Maximum I/O Pins | 16 | — |
| Dedicated Outputs | 16 | — |
| Product Terms | 160 | 160 |
| 工作温度 | 0 °C to +70 °C (Commercial) | [DATA_NEEDED: operating temperature range] |
| 封装 | 24-pin PDIP (Plastic DIP) | PLCC-28 (plastic J-lead chip carrier) |
| Technology | CMOS, UV-erasable (windowless in IPC pkg) | — |
| TTL Compatibility | 100% TTL emulation | — |
| 安装类型 | Through-Hole | Surface Mount (PLCC socket or solder) |
| MSL 等级 | [DATA_NEEDED: MSL level] | — |
| RoHS 状态 | Non-compliant (contains Pb, PDIP package) | [DATA_NEEDED: RoHS compliance] |
| Logic Capacity | Equivalent to ~24 standard 24-pin PALs | — |
| Device Family | — | Classic EPLD |
| Product Type | — | UV-Erasable / OTP PLD |
| Macrocells | — | 16 |
| Usable Gates | — | 300 |
| I/O Pins | — | 16 |
| Dedicated Inputs | — | 4 |
| 电源电压 | — | 5 V (single supply) |
| Pin-to-Pin Delay (tPD) | — | 10 ns (grade -10) |
| Counter Frequency (fCNT) | — | 100 MHz |
| Logic Family Compatibility | — | TTL (5 V CMOS/TTL-compatible I/O) |