EP610LC-30 vs EP610PC-30 比較
詳細な並列比較: EP610LC-30 メーカー: Intel および EP610PC-30 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP610LC-30 | EP610PC-30 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $16.40 | $27.74 |
| Family | Classic EPLD (EP610) | — |
| Macro Cells | 16 | — |
| Logic Gates | Equivalent to 300 gates (typical) | — |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V (4.75 V to 5.25 V) |
| Programming Voltage (VPP) | 13 V nominal | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| パッケージ | 24-pin CERDIP / PDIP | 24-pin PDIP (0.300 inch) |
| 動作温度 | 0 C to +70 C (commercial) / -55 C to +125 C (military) | 0C to +70C (commercial) |
| Erase/Program Cycles | 1000 typical | — |
| 実装タイプ | Through-Hole | Through-Hole |
| 出力タイプ | CMOS tri-state (programmable) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | Not applicable (legacy non-compliant package per distributor listing) |
| Logic Compatibility | TTL and CMOS | — |
| Turbo Mode | Yes (registered path bypass) | — |
| Device Family | — | Classic EPLD (EP610) |
| Macrocells | — | 16 |
| Usable Gates | — | 300 |
| Propagation Delay (tPD) | — | 30 ns |
| Maximum Pipeline Frequency | — | 33.3 MHz (typical) / 100 MHz pipelined |
| Process Technology | — | CMOS EPROM |
| Programmability | — | One-Time Programmable (OTP, no window on plastic PDIP) |
| Output Drive Current | — | [DATA_NEEDED: IOH/IOL per datasheet DC characteristics] |
| Input Pins (Dedicated) | — | [DATA_NEEDED: dedicated input count from datasheet pinout] |
| I/O Pins | — | [DATA_NEEDED: bidirectional I/O count from datasheet pinout] |
| Programming Tool | — | Altera A+PLUS / MAX+PLUS II (legacy) |
| Lead Free Status | — | Not applicable |
| Current Distributor | — | Rochester Electronics, LLC (authorized continuing source) |