EP610LC-30 vs EP610PC-30 Comparison

Detailed side-by-side comparison of EP610LC-30 by Intel and EP610PC-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP610LC-30 EP610PC-30
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $16.40 $27.74
Family Classic EPLD (EP610) β€”
Macro Cells 16 β€”
Logic Gates Equivalent to 300 gates (typical) β€”
Pin-to-Pin Delay (tPD) 30 ns β€”
Pipelined Data Rate up to 100 MHz β€”
Supply Voltage (VCC) 4.75 V to 5.25 V 5 V (4.75 V to 5.25 V)
Programming Voltage (VPP) 13 V nominal β€”
Technology CMOS EPROM (UV-erasable) β€”
Package 24-pin CERDIP / PDIP 24-pin PDIP (0.300 inch)
Operating Temperature 0 C to +70 C (commercial) / -55 C to +125 C (military) 0C to +70C (commercial)
Erase/Program Cycles 1000 typical β€”
Mounting Type Through-Hole Through-Hole
Output Type CMOS tri-state (programmable) β€”
RoHS Status [DATA_NEEDED: RoHS status] Not applicable (legacy non-compliant package per distributor listing)
Logic Compatibility TTL and CMOS β€”
Turbo Mode Yes (registered path bypass) β€”
Device Family β€” Classic EPLD (EP610)
Macrocells β€” 16
Usable Gates β€” 300
Propagation Delay (tPD) β€” 30 ns
Maximum Pipeline Frequency β€” 33.3 MHz (typical) / 100 MHz pipelined
Process Technology β€” CMOS EPROM
Programmability β€” One-Time Programmable (OTP, no window on plastic PDIP)
Output Drive Current β€” [DATA_NEEDED: IOH/IOL per datasheet DC characteristics]
Input Pins (Dedicated) β€” [DATA_NEEDED: dedicated input count from datasheet pinout]
I/O Pins β€” [DATA_NEEDED: bidirectional I/O count from datasheet pinout]
Programming Tool β€” Altera A+PLUS / MAX+PLUS II (legacy)
Lead Free Status β€” Not applicable
Current Distributor β€” Rochester Electronics, LLC (authorized continuing source)

Datasheets & Resources

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