EP610PC-25T vs EP610PC-25 比較
詳細な並列比較: EP610PC-25T メーカー: Intel および EP610PC-25 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Intel
EP610PC-25T - 16-Macrocell Classic EPLD, 25ns, PDIP-24 | Intel / Altera
EP610PC-25T ⚠ ラストタイムバイ仕様比較
| パラメータ | EP610PC-25T | EP610PC-25 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | ラストバイ | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $28.95 | $9.75 |
| Manufacturer | Intel (formerly Altera) | — |
| Distributor / Stocking Source | Rochester Electronics, LLC | — |
| Device Family | Altera Classic EPLD - EP610 | Classic EPLD (EP610 series) |
| Device Type | Erasable Programmable Logic Device (EPLD, OTP for plastic package) | OT PLD, PAL-type, CMOS |
| Logic Capacity | 300 usable gates | — |
| Macro Cells | 16 | 16 |
| Registers | 16 | — |
| User I/Os | 16 | — |
| Propagation Delay (tPD) | 25 ns (speed grade 25) | — |
| Maximum Toggle Frequency | [DATA_NEEDED: max fmax] | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Process Technology | ECMOS (CMOS, EPROM-based) | — |
| パッケージ | PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing) | PDIP-24 (0.3 inch, through-hole) |
| Pinout Compatibility | Pin-compatible with EP610DC-25 (CERDIP-24, windowed) | — |
| 動作温度 | 0 °C to +70 °C (commercial) | [DATA_NEEDED: operating temperature grade] |
| Programming Method | OTP (one-time programmable) via Altera programming hardware | EPROM (UV-erasable), via Altera programming hardware |
| 実装タイプ | Through-hole | Through-Hole (DIP) |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Shipping Form (T suffix) | Tube | — |
| Usable Gates | — | 300 |
| Propagation Delay (tpd) | — | 25 ns |
| Maximum Pipelined Data Rate | — | 100 MHz |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| Technology | — | CMOS, EPROM (UV-erasable) |
| Dedicated Inputs | — | 4 |
| I/O Pins | — | 20 (bidirectional, JTAG-programmable OE per macrocell) |