EP610PC-25T vs EP610PC-25 Comparison

Detailed side-by-side comparison of EP610PC-25T by Intel and EP610PC-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP610PC-25T EP610PC-25
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last_time_buy Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $28.95 $9.75
Manufacturer Intel (formerly Altera) β€”
Distributor / Stocking Source Rochester Electronics, LLC β€”
Device Family Altera Classic EPLD - EP610 Classic EPLD (EP610 series)
Device Type Erasable Programmable Logic Device (EPLD, OTP for plastic package) OT PLD, PAL-type, CMOS
Logic Capacity 300 usable gates β€”
Macro Cells 16 16
Registers 16 β€”
User I/Os 16 β€”
Propagation Delay (tPD) 25 ns (speed grade 25) β€”
Maximum Toggle Frequency [DATA_NEEDED: max fmax] β€”
Pipelined Data Rate up to 100 MHz β€”
Supply Voltage (VCC) 5 V β€”
Process Technology ECMOS (CMOS, EPROM-based) β€”
Package PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing) PDIP-24 (0.3 inch, through-hole)
Pinout Compatibility Pin-compatible with EP610DC-25 (CERDIP-24, windowed) β€”
Operating Temperature 0 Β°C to +70 Β°C (commercial) [DATA_NEEDED: operating temperature grade]
Programming Method OTP (one-time programmable) via Altera programming hardware EPROM (UV-erasable), via Altera programming hardware
Mounting Type Through-hole Through-Hole (DIP)
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Shipping Form (T suffix) Tube β€”
Usable Gates β€” 300
Propagation Delay (tpd) β€” 25 ns
Maximum Pipelined Data Rate β€” 100 MHz
Supply Voltage (Vcc) β€” 5 V (nominal)
Technology β€” CMOS, EPROM (UV-erasable)
Dedicated Inputs β€” 4
I/O Pins β€” 20 (bidirectional, JTAG-programmable OE per macrocell)

Datasheets & Resources

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