EP610PI-25 vs EP610IPC-25 比較
詳細な並列比較: EP610PI-25 メーカー: Rochester Electronics および EP610IPC-25 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Rochester Electronics
EP610PI-25 - 16-Macrocell Classic EPLD, 25ns DIP-24 | Rochester
EP610PI-25 Obsolete仕様比較
| パラメータ | EP610PI-25 | EP610IPC-25 |
|---|---|---|
| ブランド | Rochester Electronics | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $20.50 | $8.85 |
| Product Type | Erasable Programmable Logic Device (EPLD) | — |
| Series | Classic EP610 | — |
| Macrocells | 16 | — |
| Usable Gates | ~300 gates | — |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Internal Frequency (fCNT) | [DATA_NEEDED: fCNT] | — |
| Number of Dedicated Inputs | 4 | — |
| Number of Bidirectional I/O Pins | 16 | — |
| パッケージ | 24-pin DIP (PI) ceramic through-hole | 24-pin PDIP (Plastic DIP) |
| 動作温度範囲 | Industrial (I suffix): -40C to +85C | — |
| Supply Voltage (VCC) | 5 V nominal | 4.75 V to 5.25 V |
| Process Technology | CMOS, UV-erasable | — |
| Programmable Flip-Flop Modes | D, T, JK, SR (per macrocell) | — |
| Global Clock Pins | 1 | — |
| 実装タイプ | Through-Hole (DIP) | Through-Hole |
| Lead-Free / RoHS | [DATA_NEEDED: RoHS] | — |
| Original Manufacturer | Altera (now Intel PSG; legacy stock from Rochester Electronics) | — |
| Family | — | Classic EPLD (EP610) |
| Architecture | — | PAL-type, CMOS, Erasable |
| Propagation Delay (tpd) | — | 25 ns (max) |
| Maximum Inputs | — | 20 |
| Maximum I/O Pins | — | 16 |
| Dedicated Outputs | — | 16 |
| Product Terms | — | 160 |
| 動作温度 | — | 0 °C to +70 °C (Commercial) |
| Technology | — | CMOS, UV-erasable (windowless in IPC pkg) |
| TTL Compatibility | — | 100% TTL emulation |
| MSLレベル | — | [DATA_NEEDED: MSL level] |
| RoHS ステータス | — | Non-compliant (contains Pb, PDIP package) |
| Logic Capacity | — | Equivalent to ~24 standard 24-pin PALs |