EP910DC-40 vs EP910IDC-15 比較
詳細な並列比較: EP910DC-40 メーカー: Altera および EP910IDC-15 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910DC-40 | EP910IDC-15 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $13.95 | $9.95 |
| Device Family | Classic EPLD (EP910 series) | — |
| Architecture | PAL-type AND/OR, UV-erasable CMOS | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 10 |
| Bidirectional I/O Pins | 24 | — |
| Total Inputs to Logic Array | 36 | — |
| Product Terms | 240 maximum | — |
| Maximum Propagation Delay (tPD) | 40 ns | — |
| Maximum Operating Frequency (fMAX) | 25 MHz | — |
| Global Clocks | 2 | — |
| 電源電圧 | 5 V (typical for Classic EPLD family) | — |
| Operating Temperature (Commercial) | 0 °C to 70 °C | — |
| パッケージ | DIP-40 (ceramic, through-hole) | 40-pin CDIP (Ceramic DIP, through-hole) |
| 実装タイプ | Through-Hole | — |
| RoHS ステータス | [DATA_NEEDED: rohs_status] | non_compliant (ceramic DIP contains lead) |
| Programming Method | UV-erase + EPROM programmer; on-board logic test circuitry | — |
| Manufacturer | — | Altera (now Intel PSG) |
| Family | — | Classic EPLD |
| Equivalent Gates | — | 450 |
| Flip-Flops | — | 48 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Maximum Frequency (fCNT) | — | 66.6 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Terminal Count | — | 40 |
| Terminal Form | — | Through-Hole |
| Temperature Grade | — | Commercial (0C to +70C) |
| Programmable Security Bit | — | Yes |
| On-board Test Circuitry | — | Yes |
| Logic Type | — | UV Erasable EPROM-based |
| I/O Pins | — | 24 |
| Programming Technology | — | EPROM (UV-erasable) |