EP910DC-40 vs EP910IDC-15 Сравнение
Подробное сравнение бок о бок EP910DC-40 от Altera и EP910IDC-15 от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Сравнение характеристик
| Параметр | EP910DC-40 | EP910IDC-15 |
|---|---|---|
| Бренд | Altera | Altera |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Obsolete | Obsolete |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $13,95 | $9,95 |
| Device Family | Classic EPLD (EP910 series) | — |
| Architecture | PAL-type AND/OR, UV-erasable CMOS | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 10 |
| Bidirectional I/O Pins | 24 | — |
| Total Inputs to Logic Array | 36 | — |
| Product Terms | 240 maximum | — |
| Maximum Propagation Delay (tPD) | 40 ns | — |
| Maximum Operating Frequency (fMAX) | 25 MHz | — |
| Global Clocks | 2 | — |
| Напряжение питания | 5 V (typical for Classic EPLD family) | — |
| Operating Temperature (Commercial) | 0 °C to 70 °C | — |
| Корпус | DIP-40 (ceramic, through-hole) | 40-pin CDIP (Ceramic DIP, through-hole) |
| Тип монтажа | Through-Hole | — |
| Статус RoHS | [DATA_NEEDED: rohs_status] | non_compliant (ceramic DIP contains lead) |
| Programming Method | UV-erase + EPROM programmer; on-board logic test circuitry | — |
| Manufacturer | — | Altera (now Intel PSG) |
| Family | — | Classic EPLD |
| Equivalent Gates | — | 450 |
| Flip-Flops | — | 48 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Maximum Frequency (fCNT) | — | 66.6 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Terminal Count | — | 40 |
| Terminal Form | — | Through-Hole |
| Temperature Grade | — | Commercial (0C to +70C) |
| Programmable Security Bit | — | Yes |
| On-board Test Circuitry | — | Yes |
| Logic Type | — | UV Erasable EPROM-based |
| I/O Pins | — | 24 |
| Programming Technology | — | EPROM (UV-erasable) |