EP910DI-30 vs EP910IDC-15 比較
詳細な並列比較: EP910DI-30 メーカー: Rochester Electronics および EP910IDC-15 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Rochester Electronics
EP910DI-30 - 24-Macrocell EPLD, 30ns, CDIP-40 | Altera (Rochester)
EP910DI-30 Nrnd仕様比較
| パラメータ | EP910DI-30 | EP910IDC-15 |
|---|---|---|
| ブランド | Rochester Electronics | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $17.60 | $9.95 |
| Product Type | UV-Erasable Programmable Logic Device (EPLD) | — |
| Family | Classic EPLD (Altera EP910 series) | Classic EPLD |
| Macrocell Count | 24 | — |
| Propagation Delay (tpd) | 30 ns | — |
| Maximum Toggle Frequency (fmax) | 62 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V |
| Technology | CMOS, UV-erasable EPROM | — |
| パッケージ | CDIP-40 (ceramic DIP, 40-pin with UV window) | 40-pin CDIP (Ceramic DIP, through-hole) |
| 実装タイプ | Through-Hole (DIP) | — |
| Dedicated Inputs | 10 | 10 |
| Dedicated I/O Pins | 12 (12 input + 12 output) | — |
| Output Enable Pins | 2 | — |
| ピン数 | 40 | — |
| Programmable Logic Element | JEDEC fuse map (3rd-party programmer) | — |
| 動作温度 | -40C to +85C (industrial) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | non_compliant (ceramic DIP contains lead) |
| Manufacturer (Original) | Altera (now Intel PSG) | — |
| Current Distributor / Authorized Aftermarket | Rochester Electronics, LLC | — |
| Manufacturer | — | Altera (now Intel PSG) |
| Equivalent Gates | — | 450 |
| Macrocells | — | 24 |
| Flip-Flops | — | 48 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Maximum Frequency (fCNT) | — | 66.6 MHz |
| Terminal Count | — | 40 |
| Terminal Form | — | Through-Hole |
| Temperature Grade | — | Commercial (0C to +70C) |
| Programmable Security Bit | — | Yes |
| On-board Test Circuitry | — | Yes |
| Logic Type | — | UV Erasable EPROM-based |
| I/O Pins | — | 24 |
| Programming Technology | — | EPROM (UV-erasable) |