EP910DI-30 vs EP910IDC-15 对比
详细并排对比 EP910DI-30 出自 Rochester Electronics 和 EP910IDC-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Rochester Electronics
EP910DI-30 - 24-Macrocell EPLD, 30ns, CDIP-40 | Altera (Rochester)
EP910DI-30 Nrnd规格对比
| 参数 | EP910DI-30 | EP910IDC-15 |
|---|---|---|
| 品牌 | Rochester Electronics | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $17.60 | $9.95 |
| Product Type | UV-Erasable Programmable Logic Device (EPLD) | — |
| Family | Classic EPLD (Altera EP910 series) | Classic EPLD |
| Macrocell Count | 24 | — |
| Propagation Delay (tpd) | 30 ns | — |
| Maximum Toggle Frequency (fmax) | 62 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V |
| Technology | CMOS, UV-erasable EPROM | — |
| 封装 | CDIP-40 (ceramic DIP, 40-pin with UV window) | 40-pin CDIP (Ceramic DIP, through-hole) |
| 安装类型 | Through-Hole (DIP) | — |
| Dedicated Inputs | 10 | 10 |
| Dedicated I/O Pins | 12 (12 input + 12 output) | — |
| Output Enable Pins | 2 | — |
| 引脚数量 | 40 | — |
| Programmable Logic Element | JEDEC fuse map (3rd-party programmer) | — |
| 工作温度 | -40C to +85C (industrial) | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance status] | non_compliant (ceramic DIP contains lead) |
| Manufacturer (Original) | Altera (now Intel PSG) | — |
| Current Distributor / Authorized Aftermarket | Rochester Electronics, LLC | — |
| Manufacturer | — | Altera (now Intel PSG) |
| Equivalent Gates | — | 450 |
| Macrocells | — | 24 |
| Flip-Flops | — | 48 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Maximum Frequency (fCNT) | — | 66.6 MHz |
| Terminal Count | — | 40 |
| Terminal Form | — | Through-Hole |
| Temperature Grade | — | Commercial (0C to +70C) |
| Programmable Security Bit | — | Yes |
| On-board Test Circuitry | — | Yes |
| Logic Type | — | UV Erasable EPROM-based |
| I/O Pins | — | 24 |
| Programming Technology | — | EPROM (UV-erasable) |